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A scientific study of the problems of digital engineering for space flight systems,
with a view to their practical solution.


Section 1.2 Introduction

ACTEL-designed Field Programmable Gate Arrays (FPGA's) manufactured by Matsushita Electronics Corporation have been evaluated for their suitability in space applications.   The FPGA's are manufactured on a commercial manufacturing process as opposed to a radiation-hardened manufacturing process.  A number of design and cost tradeoffs make the commercial FPGA an attractive alternative to other ASIC technologies.  The short design cycle and relatively low cost are an immediate advantage.  ACTEL's proven oxide-nitride-oxide antifuse reliability also warranted looking at these FPGA's for space applications.

The areas of special interest and evaluation conducted by JPL and others included metallization integrity, radiation tolerance from total dose damage, single event effects sensitivity, and device latchup caused from heavy ions.  In addition a number of parts were put on life test.  They were examined using destructive physical analysis methods before and after 2000 hr of life.  From some of the data and analysis some lifetime predictions were made within the constraint of design rules and particular application.  Because the ACTEL FPGA is not manufactured on a radiation-hardened process, it is important to review the results in light of the inherent capabilities of the device and design with the current process technology.  With this in mind, some standard benchmark can be established to give the user some guidance for performance.   The results reported to not always agree because test methods and device configurations were not identical.  However, based on the data obtained and assimilated an expected level of behavior can be predicted for the FPGA devices.  It is up to the user to do further testing if needed to satisfy a more stringent requirement.   This report and its findings in general support the ACTEL FPGA technology for some space applications and conditions.

The report is divided into four sections.  The first section is the general section comprising the general comments and conclusions by JPL.  The remaining sections are a summary of the work and supporting data for the A1020 (2-µm), A1280 (1.2 µm), and the A1020A (1.2 µm) FPGA's.  The sources and authors for these summaries are referenced.  The work was done independently yet together completes the objective to evaluate the FPGA technology.  The technical content of the charts and graphs is presented exactly as taken from the sources.  Interpretation is left to the reader because the data were from limited sample sizes, which may not be statistically valid.


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Last Revised: January 09, 2002
Digital Engineering Institute
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