NASA Office of Logic Design

A scientific study of the problems of digital engineering for space flight systems,
with a view to their practical solution.

Papers from the

2003 IEEE Nuclear and Space Radiation Effects Conference

Monterey, California
July 2003

Program

Late news papers

A Selection of Papers

PA-1: Bulk Damage Caused by Single Protons in SDRAMs Satoshi Kuboyama, Hiroyuki Shindou, Yasushi Deguchi, Sumio Matsuda, NASDA; Toshio Hirao, JAERI	Abstract We describe experimental data for a new failure mode that has a cross-section larger than SEU in 256 Mbit SDRAMs. The failure mode is attributable to the bulk damage caused by single protons.
PA-5 Utilizing Asynchronous Logic for Performance Improvement in Space Applications David J. Barnhart, United States Air Force Academy; Paul W. Duggan, Bruce W. Suter, Air Force Research Laboratory; Kenneth S. Stevens, Intel Corp.	Abstract Asynchronous logic is used in the design of prototype Fast Fourier Transform processors for space applications to increase throughput and efficiency. Total dose characterization reveals the potential for strategic applications.
D-2 Comparisons of Soft Error Rate for SRAMs in Commercial SOI and Bulk below the 130 nm Technology Node Philippe Roche, Gilles Gasiot, STMicroelectronics; Keith Forbes, Vincent O'Sullivan, Motorola; Veronique Ferlet, CEA-DAM	Abstract This paper presents experimental ASER on SOI and bulk SRAMs for the 250, 130 and 90 nm technologies. Monte Carlo simulations are used to model the key parameters for cosmic and terrestrial SER towards the 65 nm node.
PD-2 Soft Error Rate Increase for New Generations of SRAMs Thomas Granlund, Bo Granbom, Saab Avionics AB; Nils Olsson, Systems Technology; Swedish Defence Research Agency	Abstract We report on enhanced susceptibility for neutron-induced soft errors from accelerated testing of Static Random Access Memories (SRAMs), performed at Los Alamos National Laboratory. This enhancement is per bit of memory.
E-1 Modeling Single-Event Transient Propagation in a Complex Digital Device Ken Clark, US Naval Research Laboratory	Abstract A methodology to determine the effect of SETs on complex digital devices has been developed. This methodology is based on the SET state-transition model and was validated by radiation testing of a complex digital device.
E-3 Identification and Classification of Single Event Upsets in the Configuration Memory of SRAM based FPGAs Marco Ceschia, Alessandro Paccagnella, Damiano Bortolato, Paolo Zambolin, Università di Padova; Massimo Violante, Matteo Sonza Reorda, Paolo Bernardi, Maurizio Rebaudengo, Politecnico di Torino; Marco Bellato, Andrea Candelori, Istituto Nazionale di Fisica Nucleare	Abstract SRAM based FPGA has been tested under heavy ion irradiation. Single event upsets in the configuration memory have been identified and classified to develop a fault injection model that simulates the effects of SEUs on implemented designs.
E-4 Single Event Effects in SOI CMOS 4M SRAM Fabricated in Unibond Michael Liu, Walter Heikkila, Keith Goelke, Dany Anthony, Allan Hurst, Gary Kirchner, Honeywell SSEC; William Jenkins, Harold Hughes, Naval Research Laboratory; Souvick Mitra, Dimitris Ioannou, George Mason University	Abstract Single event upsets in 4M SRAM fabricated in Unibond substrates are measured and discussed. Critical charge calculated from heavy ion data is compared with SPICE simulation. Improved SEU performance with beta reduction will be reported.
E-5 Impact of Data Cache Memory on the SEU Induced Error Rate of Microprocessors Fabien Faure, Raoul Velazco, Joan Albert Gimeno Rovira, TIMA-CMP; Massimo Violante, Maurizio Rebaudengo, Matteo Sonza Reorda, Politecnico di Torino	Abstract Cache memories included in most complex processors constitute a significant contribution to the global SEU induced error rate. Three different approaches allowing the study of this contribution by fault injection are investigated in this paper.
E-6 Single-Event Upset in Advanced Commercial PowerPC Microprocessors Farokh Irom, Farhad F. Farmanesh, Gary M. Swift, Allan H. Johnston, Jet Propulsion Laboratory	Abstract Single-event upset from heavy ions is measured for advanced commercial microprocessors, comparing upset sensitivity in registers and d-cache for several generations of devices. Multiple-bit upsets and asymmetry in register upset cross sections are also discussed.
PE-4 Single-Event Effects in 0.18 µm CMOS Commercial Processes Akiko Makihara, Hiroaki Asai, Yasuo Sakaide, Yoshihisa Tsuchiya, Toshifumi Arimitsu, High-Reliability Components Corporation; Yoshiya Iide, Hiroyuki Shindou, Satoshi Kuboyama, Sumio Matsuda, National Space Development Agency of Japan	Abstract We evaluated SEEs in sample circuits fabricated at TSMC and Fujitsu with their 0.18 µm CMOS commercial processes. The samples were designed with hardness-by-design methodology. The results indicate effective hardening design associated with SEEs.
PE-5 SEU Mitigation for Half-Latches in Xilinx Virtex FPGAs Paul Graham, Michael Caffrey, Los Alamos National Laboratory; Michael Wirthlin, D. Eric Johnson, Nathan Rollins, Brigham Young University	Abstract We introduce the half-latch single-event upset issue found in Xilinx Virtex FPGAs and describe methods for mitigating the effects of half-latch SEUs. One mitigation method’s effectiveness is then illustrated through experimental data.
PE-6 Validation of an FPGA Fault Simulator Michael J. Wirthlin, Eric Johnson, Nathan Rollins, Brigham Young University; Paul Graham, Michael Caffrey, Los Alamos National Laboratory	Abstract This work describes the radiation testing for validating a fault simulation tool used to study the behavior of FPGA circuits in the presence of configuration memory upsets.
PE-7 Single Event Effects and Mitigation in Commercial 0.15 µm Antifuse-Based FPGA Jih-Jong Wang, Brian Cronquist, John McCollum, Solomon Wolday, Actel Corporation; Rich Katz, NASA/Goddard; Igor Kleyner, Orbital Science Corporation	Abstract The single event effects of 0.15 µm antifuse FPGA were investigated by beam test and computer simulation. Single event upsets of user flip-flop, clock, control logic, and embedded SRAM are identified and mitigation methods are proposed.
F-3 Data Retention After Heavy Ion Exposure of Floating Gate Memories: Analysis and Simulation Luca Larcher, Università di Modena; Giorgio Cellere, Alessandro Paccagnella, Università di Padova; Andrea Chimenton, Università di Ferrara; Andrea Candelori, INFN; Alberto Modelli, ST Microelectronics	Abstract Irradiated floating gates present large tails in distributions of threshold voltages during data retention experiments. A model which statistically accounts for gate oxide currents due to phonon and trap assisted tunneling closely describes experimental data.
PH-2 Heavy-Ion Single Event Effects Testing of Lead-On-Chip Assembled High-Density Memories R. Harboe-Sørensen, European Space Agency/ESTEC; F.-X. Guerre, J.-G. Loquet, C. Tizon, Hirex Engineering	Abstract This paper summarizes steps taken by ESA in order to address heavy ion SEE testing of lead-on-chip assembled high-density memories. In particular sample preparation techniques, test approaches, test facilities and test analyses will be addressed.
PI-5 Microdose Analysis of Ion Strikes on SRAM Cells Leif Scheick, JPL/NASA	Abstract The effect of ion radiation on SRAM microstructures is analyzed. The voltage at which a cell cannot hold a programmed state changes with microdose. SPICE simulations and physical analyses support experimental data.
W-4 Total Dose, Single Event Effect and Radiation Induced Single Cell Failures in Advanced Flash Memories Duc Nguyen, Leif Scheick, JPL/NASA	Abstract We compare radiation effects on the highest density multi-level cell NOR and single-level cell NAND flash memories to the previous generations. Total ionization dose (TID) test results show unexpected failure modes.
W-5 Recent Radiation Test Results at JPL Bruce E. Pritchard, Bernard G. Rax, Steven S. McClure, NASA-Jet Propulsion Lab	Abstract This paper documents recent TID test results (including proton damage and ELDRS) obtained by JPL. Unusual test results, such as abnormally low or high failure levels or unusual failure or response mechanisms, are emphasized.
W-12 SEE Sensitivity Trends in Non-Hardened High Density SRAMs with Sub-Micron Feature Sizes R. Koga, K. Crawford, P. Yu, S. Crain, V. Tran, The Aerospace Corporation	Abstract The range of SEE sensitivity in non-hardened high-density SRAMs is large. Within this range, we have observed a tendency toward reduced SEU and SEFI sensitivities, as well as various cell structures, and high latchup cross-sections.
W-14 SEU Mitigation of Xilinx Virtex II FPGAs for Critical Flight Applications Candice C. Yui, Gary M. Swift, JPL/Caltech; Carl Carmichael, Xilinx, Inc.	Abstract The speed, I/O count, and reconfigurability of SRAM-based FPGAs make them attractive for flight applications. However, critical designs require effective upset mitigation. Measurements of the effectiveness of configuration control and TMR during heavy-ion irradiation are reported.
W-15 Single Event Effects Test Results of 512M SDRAMs Tilan E. Langley, Ty Morris, SEAKR Engineering, Inc.; Rocky Koga, The Aerospace Corporation	Abstract Single event effects tests results for new 512M SDRAMs are reported in this paper. Effects characterized during testing include upset, latchup, SEFI and microlatch measurements.
W-16 In-Flight Observations of Long-Term Single Event Effect Performance on Orbview-2 and Xray Timing Explorer Solid State Recorders Christian Poivey, SGT-Inc; Janet L. Barth, Kenneth A. LaBel, Harvey Safren, NASA-GSFC; George Gee, SFT-Inc.	Abstract We present multi-year SEU flight data on Solid State Recorder (SSR) memories for two NASA missions. Actual SEU rates are compared to the predicted rates based on ground test data and environment predictions.
W-17 Single Event Upset Characterization of a Personal Computer Micro-Controller System-on-a-Chip using Proton Irradiation David M. Hiemstra, Simon Yu, Marius Pop, MDRobotics	Abstract Experimental single event upset characterization of a personal computer micro-controller system-on-a-chip using proton irradiation is presented. Results are compared with previous tests on other x86 microprocessors.
PA-9L Chalcogenide Memory Arrays: Recent Radiation Effects Test Results John Rodgers, Laura Burcin, BAE Systems; Jon Maimon, Ovonyx Inc.; Ken Hunt, AFRL	Abstract BAE Systems has fabricated 64-kbit GeSbTe (chalcogenide) memories in a radiation-hardened CMOS technology. Recent radiation test results show this to be a viable solution for high-density, low-power, fast, non-volatile, radiation-hardened memories for future spacecraft applications.
W-26 Single Event Effects Hardening and Characterization of Honeywell's RHPPC Processor Integrated Circuit J. P. Lintz, L. F. Hoffmann, D. J. Bastyr, G. R. Brown, D. K. Nelson, Honeywell Defense and Space Electronic Systems	Abstract We describe SEE testing of Honeywell's radiation-hardened RHPPC Processor chip, which is functionally and pin-compatible with the commercial PowerPC 603eTM. Results support an upset rate of 1.1x10-5 upsets/chip-day in geosynchronous orbit.
W-27 Proton Irradiation Testing of ATMEL 68360 Processor and GaAs MMICS J. Seon, S. H. Min, K. W. Min, T. J. Cheong, H. J. Chun, SaTReCi; S. J. Kim, KAIST; Y. M. Kim, J. W. Park, ETRI	Abstract A summary of the proton irradiation testing for ATMEL 68360 processor and GaAs MMICs is provided. The results show sufficient qualifications of the components for Korean space missions.

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