A scientific study of the problems
of digital engineering for space flight systems,
with a view to their practical solution.
Temporally Redundant Latch For Preventing Single Event Disruptions In Sequential Integrated Circuits
Dr. David G. Mavis
Mission Research Corporation
MRC Microelectronics
1720 Randolph Road SE
Albuquerque, NM 87106-4245
505-768-7632
505-768-7601 – fax
e-mail: dgmavis@mrcmicroe.com
Paul H. Eaton
Mission Research Corporation
MRC Microelectronics
1720 Randolph Road SE
Albuquerque, NM 87106-4245
505-768-7626
505-768-7601 – fax
e-mail: peaton@mrcmicroe.com
Abstract
As the microelectronics industry has advanced, integrated circuit (IC) designs have experienced dramatic increases in both density and speed. The reason for these increases is largely due to the decreasing feature sizes with which these devices can be manufactured. (By the feature size of a given manufacturing technology, we refer to the minimum gate length of a CMOS transistor in that technology.) These advances are not without serious implications for microelectronics used in space applications where ICs are subjected to hostile environments that result in total ionizing dose effects primarily due interactions with trapped electrons and protons as well as single event effects (SEE) primarily do to interactions with cosmic rays (high energy heavy ions), high energy protons, and high energy neutrons. Of these effects, SEUs (single event upsets) represent the radiation-induced hazard most difficult to avoid in spaceborne microelectronics systems.
In this report we consider bulk CMOS (complimentary metal oxide silicon) device technologies and their response to the cosmic ray environment of space. (We are not addressing here any specific total-dose issues.) The threefold purpose of this report is to:
We will first provide some background to the reader in the area of SEU mechanisms and describe their implications for present day spaceborne microelectronics. We will then discuss an emerging SEU mechanism that will begin to impact the operation space systems fabricated in the next one or two generations of technology. Problems with using conventional approaches to harden future generations of ICs will also be discussed, particularly with regard to incompatibilities of these approaches with automated design synthesis and layout tools.
The remainder of this paper will then present and describe a new temporal sampling latch approach that is inherently immune at any technology feature size to both present day upset mechanisms and to emerging upset mechanisms. The new approach not only addresses upsets in latches, but also addresses upsets caused by transients in combinatorial logic, global clock signals, and global control signals. The new approach, when applied with special latches and a lower clock frequency can also eliminate multiple bit upsets in sequential circuit designs. Finally, since the resulting circuit is inherently SEU hard, the new approach lends itself naturally for use with automated design tools.
Table of Contents
I. Introduction
II. Background
III. An Emerging SEU Mechanism
IV. Conventional Hardening to SETs
V. ASIC Design Synthesis
VI. Temporal Sampling Latch
A. Latch Construction
B. Clocking Scheme
C. Circuit Operation
D. Elimination of Upsets
E. Clock Generation
F. Fast Mode Operation
G. Speed Tradeoff
H. Size Tradeoff
I. Scan Chain Testing
J. Static Data Storage
K. Miscellaneous Considerations
L. Connection to Design Synthesis
VII. Multiple Bit Heavy Ion Strikes
A. Type 1
B. Type 2
C. Type 3
VIII. Summary
IX. References
List of Figures
- Charge Collection due to an Ion Passing through a Junction.
- Critical Transient Width vs. Feature Size for Unattenuated Propagation.
- Typical Sequential Circuit Topology.
- Temporal Relationship for Latching a Data SET as an Error.
- Temporal Relationship for a Clock SET to Cause an Error.
- Temporal Sampling Latch with Sample and Release Stages.
- Temporal Latch Control Clocks Derived from Master Clock.
- Sample Node Values for One Computation Cycle.
- Simple (Non-SEU Immune) Control Clock Generator Circuit.
- Final SEU Immune Control Clock Generator Circuit.
- Circuit to Select Between SEU Immune and Fast Modes of Operation.
- Scan Chain Testing Approach for the Error Immune Temporal Latch.
- Shift Register Configuration to Self Scrub Errors for Statis Data Storage.
Summary
We have described a new and innovative temporal sampling latch design approach which can be easily applied to any sequential circuit. The design approach achieves total upset immunity to any single node cosmic ray strike occurring anywhere in the circuit and at any time within a clock cycle. Since the approach itself is inherently immune to these effects, spaceborne microelectronics can be designed with conventional (non-SEU hardened) standard cell libraries using conventional (non-SEU cognizant) design synthesis tools. Speed (2´) and area (30%) tradeoffs of the approach are minor considering that total SEU immunity is achieved.
Not only are the usual static latch SEUs eliminated, but upsets due to SETs in the combinatorial logic, global clock, and global control signals are also eliminated. Designs using the temporal sampling latch are therefore immune at any technology features size, both present and future.
The temporal sampling latch can also be implemented with special latches and operated at slower clock speeds to additionally achieve immunity to multiple node cosmic ray strikes. Since multiple node strike cross sections are small, these special techniques may be necessary for only a limited number of spaceborne and high-altitude microelectronics applications (such as life-critical systems).
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