PROGRAMMABLE TECHNOLOGIES WEB SITE

A scientific study of the problems of digital engineering for space flight systems,
with a view to their practical solution.

 

Irradiation of a FPGA in a Submicron CMOS Process


Abstract

We have measured the effects of total ionizing dose on a XC4036XL-1HQ240C. The FPGA operated without error for 115 days while being irradiated with a dose rate if 87 rad(Si)/hr. A total dose of (236 ± 14) krad(Si) was absorbed before the first error occurred.

Table of Contents

    1. Introduction
    2. Test Procedure
    3. Results
    4. Summary and Discussion
    1. Setup of the Experimental
    2. A.1 Geometry and Positions of the Dosimeters
      A.2 FPGA Socket
      A.3 Circuit Error Checks

    3. Dosimetry

B.1 Dose Rate in the Dosimeters
        B.1.1 Absorption Measurements
        B.1.2 Uncorrected Dose Rate
B.2 Corrections to the Dose Rate
        B.2.1 Aperture Correction
        B.2.2 Energy Absorption Correction
        B.2.3 Distance Correction
        B.2.4 Attenuation Correction
B.3 Dose Rate in the FPGA
B.4 Total Absorbed Dose
        B.4.1 Source Decay Correction
        B.4.2 Total Corrected Absorbed Dose

List of Figures

Figure 1. Power supply current versus accumulated dose.

Figure 2. Total number of address sequence errors versus time after the first error.

Figure 3. Total number of hard errors versus time after the first error.

Figure 4. Power supply current versus time during annealing.

Figure 5. Power supply current versus time during the entire test.

Figure 6. Geometry and position of the dosimeters. Not to scale. Dimensions in millimeters.

Figure 7. Geometry of the experiment as seen from the source. Not to scale. Dimensions in millimeters.

Figure 8. FPGA Socket.

Figure 9. Absorption difference versus time for dosimeters in front and behind the FPGA. The curves are straight-line fits to the data. The error bars are too small to be seen.

List of Tables

Table 1. Absorption Measurements. The error in the absorption measurements is ±0.0003.

Table 2. Measurements and corrections used in the dose calculations.

Conclusions

Figure 5 shows the power supply current versus time during the entire test. Buring periods of irradiation (current increasing) the configuration file was loaded. During periods of annealing (current decreasing) the configuration was not loaded but the chips was still under bias.

The FPGA was irradiated at a dose rate of (87 ± 5) rad(Si)/hr. The current increased after 30 days ((63 ± 4) krad(Si)). This increase was probably due to the onset of leakage currents. The first error occurred after 115 days **236 ± 14) krad(Si)). This was a soft error which was reset without reloading the circuit configuration.

After the first error, the soft error rate was about one every 29 min for about 19 hr. The error rate then increased to about one every 25 s for the next 10 hr until the radiation source was removed. All these errors could be cleared by a reset without reloading the circuit configuration.

After almost 20 hr of soft errors the first hard error occurred. This error required a reload of the circuit configuration. The hard error rate was on average about one every 24 min until we stopped irradiation, 9hr after the first hard error.

A repeated cycle of irradiation and annealing showed similar operating behavior to the first cycle. The current increased slowly during irradiation and dropped slowly during annealing. If no misalignment of the apparatus took place during re-installation, the FPGA received an additional 54 krad(Si) for a total of approximately 290 krad(Si). Several intermittent errors occurred after about 23 additional kilorad and during a manual survey of the radiation zone.

We believe the leakage currents increased until a logic failure occurred. All attempts to download the circuit configuration were successful and hence there was no indication of a failure with the SRAM configuration switches. After irradiation we looked for increased address skew on the outputs and a change in rise time. No evidence was found for any change and hence the radiation damage did not effect the I/O blocks of the FPGA. Due to the limited aperture of the setup, the I/O blocks may not have received significant radiation. The power supply current was high even when the circuit configuration was not loaded and hence the radiation damage was a static effect.


Home
Last Revised January 09, 2002
Digital Engineering Institute
Web Designer: Richard Katz