Ben Cohen
VhdlCohen Publishing
http://www.vhdlcohen.com/
vhdlcohen@aol.com
January 3, 2001
Abstract
This paper presents a technique, which uses the user-defined resolution function feature of VHDL, to selectively control from VHDL the assertion of errors imposed on testbench signals of type Std_Logic. This technique allows the testbench environment to selectively inject errors at specific times and with specific values onto signals to verify the design-under-test responses to interface errors.
Table of Contents
1. Introduction
2. Use of User-Defined Resolution Function
2.1 Method of Operation
2.2 Application Example
List of Figures
Figure 1. Incorrectly Attempting to Force a Value onto a Bus
Figure 2. Forcing a Value onto a Bus with Resolved Record Type
Figure 2.2-1. Test Component
Figure 2.2-2. Testbench with Error Injection
Figure 2.2-3. Simulation Results
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