A scientific study of the problems
of digital engineering for space flight systems,
with a view to their practical solution.
Internal Testing of Programmable Circuits
Romain Desplats, Philippe Perdu
CNES-SOREP laboratory - 18 avenue Edouard BELIN - 31401 Toulouse Cedex 4 - FRANCE
tel: (+33) 561.28.17.87 fax: (+33) 561.27.47.32
email: Romain.Desplats@cnes.fr
Abstract
The growing use of programmable circuits has made it necessary to perform accurate debug and internal testing of these circuits. To meet this challenge, we have developed an innovative method to investigate the internal functionality of programmable circuits.
Table of Contents
1. Introduction
2. FPGA Architecture
2.1 Routing architecture
2.2 Antifuse technology
3. Internal testing challenge of FPGA circuits
4. FPGA layout generation
5. Automatic signal extraction
6. Conclusion
List of Figures
Figure 1. Global view of an Actel A14100 in a cavity-down package. The large die size and the high pin number are visible.
Figure 2. Actel A1280 and A14100 FPGA circuit profiles. These two components have good radiation tolerance and high performance which make them excellent candidates for space and military programs [2].
Figure 3. Generalized Floor Plan of ACT 3 Device [3].
Figure 4. Logic Module Interconnection [4].
Figure 5. Programmable Interconnect [4]. Antifuses (normally open structures) are programmed to connect logic modules.
Figure 6. Physical representation of an antifuse [5].
Figure 7. Antifuse programming [6]. Antifuse structures offer several advantages such as high speed and highly reliable structures adapted to endure space environments.
Figure 8. FPGA programming flow - From descriptive behavior to programming. The circuit can be designed using VHDL for example and, after synthesis a fuse file is generated. The file corresponds to the programming of the circuit.
Figure 9. FPGA Internal testing challenge: The metal lines on the large surface of an Actel A14100 corresponding to the net of interest (net57 here) have to be located.
Figure 10. Linked navigation between the netlist (left), the layout (right) and the FPGA programmed circuit.
Figure 11. Generation of a generic layout for an FPGA circuit from images taken with an optical microscope.
Figure 12. Cell location of an FPGA circuit linked to the netlist –The cell of interest superimposed on the SEM image of the circuit appears in the lower center of the figure.
Figure 13. SSVC image - The signal for the selected cell (on the left) appears in black (on the right) in the SSVC image. All other signals have been filtered out.
Figure 14. Electron Beam Testing at the equipotential of interest, metal line that have been located on the SSVC image; the voltage contrast measure can be compared to simulation.
Conclusions
The exploding use of FPGA circuits to replace ASICs for logic applications in many fields including space programs such as satellites has generated a growing demand for debug of FPGA circuits. It is increasingly necessary to be able to validate the internal behavior of FPGA circuits under specific stressful environments. This requires visibility and testability of FPGA circuits which by nature are not very accessible.
In order to meet this challenge, we have developed a complete method based on the generation of a layout for any programmed FPGA. This method can be implemented on Electron Beam Testers and does not require any hardware modifications. It allows fast and precise localization of any specific signals found in the netlist (electrical description of the programmed circuit). Then, accurate measurements can be performed with respect to simulation, leading to in-depth internal testing of FPGA circuits.
This new method offers optimization of sensitive designs and contributes to a better understanding of FPGA internal behavior under specific environments.
Home
Last Revised January 09, 2002
Digital Engineering Institute
Web Designer: Richard Katz