A scientific study of the problems
of digital engineering for space flight systems,
with a view to their practical solution.
Eduardo Bezerra 1, Fabian Vargas 2, Ahmet Ozcerit 3
and Michael Paul Gough 4
1, 3, 4 Space Science Centre
School of Engineering
University of Sussex
BN1 9QT, England
E.A.Bezerra@sussex.ac.uk
A.Ozcerit@sussex.ac.uk
M.P.Gough@sussex.ac.uk
1
Faculty of Informatics2
Electrical Engineering Dept.Abstract
In this work, strategies for dependability improvement of embedded systems based in configurable computing technology are discussed. To better explore the possibilities, an embedded system for space application was chosen as a case study. The case study was first implemented in a high level of abstraction, using the VHDL language, targeting its utilisation in a situation where no fault tolerant requirements were needed. The requisites to increase the reliability and testability of this system are discussed here, as well as some expected results.
Table of Contents
List of Figures
Figure 1. Block diagram of FTSVAL-VHDL (and SVAL-VHDL) hardware components.
Figure 2. VHDL code for one voter, and block diagram of the voters and application inside the FPGA.
Figure 3. Block diagram of FTSVAL-VHDL, with extra external hardware components.
Figure 4. The reliability responses for each architecture against time.
List of Tables
Table 1. Performance comparison for the ACF application.
Conclusions and Future Work
Some possibilities for dependability improvement introduced by the configurable computing technology, were discussed in this paper. In sections 3 and 4 were described strategies for preventing SEU effects and to mask connectivity faults of the case study. In section 5 a new approach to estimate system testability and to determine the minimum test vector set based on an adaptation of the weak mutation analysis technique was discussed. In section 6, the expected system reliability and performance improvements were shown.
The strategies described in this paper deserve a deeper investigation, in order to be used in the design of a fault-tolerant on-board instrument processing system, entirely based on configurable computing. During the case study implementation (SVAL-VHDL), a series of problems related to the development of FPGA based systems arose. For instance, the synthesis tools available for high level languages (e.g. VHDL behavioural and Verilog) are still not efficient, and a VHDL developer has to follow strict rules to obtain good results [24]. An FPGA configuration bitstream generated from a high level language is space consuming, and represents a lower performer circuit when compared to one generated from schematic diagrams or low level languages such as VHDL structural. Another concern is the time necessary for Electronic Design Automation (EDA) tools to generate configuration bitstreams. In time critical systems, such as space applications, effective development facilities are important because of the short time available for making remedial changes to a faulty application. In the past several missions were saved as a result of the rapid problem identification, followed by the development of a solution, ground tests and timely transmission of the new software to the spacecraft computer.
In addition to the selection of efficient EDA tools, another investigation to be done is related to the hardware description language subject. A possibility for future FPGA designs is to use Java with preoptimised cores [25]. An important point to highlight, is that the use of a unique description format, as stated before, can improve the system dependability with the use of the above strategies from the very early design stages [9][26]. After selecting the language and the EDA tools, the next step will be the implementation of an FTSVAL-VHDL prototype, in order to determine the feasibility of the faulttolerant strategies proposed here.
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