A scientific study of the problems
of digital engineering for space flight systems,
with a view to their practical solution.
A new high density and very low cost reprogrammable FPGA architecture
Sinan Kaptanoglu, Greg Bakker, Arun Kundu, Ivan Corneillet
Actel Corporation
955 East Arques Avenue, Sunnyvale CA 94086
email: {sinan,gwb,kundu,ivan}@actel.com
Ben Ting
BTR Inc.
20410 Town Center Lane, Suite 210, Cupertino CA 95014
Abstract
A new reprogrammable FPGA architecture is described which is specifically designed to be of very low cost. It covers a range of 35K to a million usable gates. In addition, it delivers high performance and it is synthesis efficient. This architecture is loosely based on an earlier reprogrammable Actel architecture named ES. By changing the structure of the interconnect and by making other improvements, we achieved an average cost reduction by a factor of three per usable gate. The first member of the family based on this architecture is fabricated on a 2.5V standard 0.25m CMOS technology with a gate count of up to 130K which also includes 36K bits of two port RAM. The gate count of this part is verified in a fully automatic design flow starting from a high level description followed by synthesis, technology mapping, place and route, and timing extraction.
Table of Contents
1. Abstract
2. Overview
3. The FPGA Architecture3.1 The Top Level of the Hierarchy
3.2 The Middle Hierarchy3.2.1 B16x16 and its Interconnect
3.2.2 B2x2 and its Interconnect3.3 The Lowest Level of the Hierarchy
3.3.1 The Choice of Logic Modules
3.3.2 The Logic Content of the B1 Block
3.3.3 The Interconnect for the B1 Block3.4 Delays for General Routing Resources
3.5 Global and Other Utility Signals
3.6 Other Architectural Features3.6.1 DLL and Clock-doubler
3.6.2 Power Supplies
3.6.3 I/O
3.6.4 JTAG4. Design Flow and Software
4.1 Synthesis and Technology Mapping
4.2 Hard Macro Support
4.3 Place and Route Results
4.4 System Debug5. Concluding Remarks
6. Acknowledgements
7. Appendix: Estimating Routing Area for LUT-k Blocks
8. References
List of Figures
Figure 1. Floorplan of a 4-tile FPGA
Figure 2. F-Tabs
Figure 3. B16x16
Figure 4. B2x2
Figure 5. B1 Block
Figure 6. LM and BC extensions
Figure 7. B8x8 Utilities
List of Tables
Table 1. Technology mapping to LUT3
Table 2. Routing Resources
Table 3. Technology Mapping to LUT3 and LUT4
Conclusions
In conclusion, we presented some details of our new architecture, which attempts to combine the best features of both the linear mesh type routing structures and the hierarchical ones, while suppressing the less desirable effects of both, in very large and high performance FPGAs.
During the development of this architecture, we discovered, somewhat to our own surprise, that the LUT3s as building blocks have become as efficient as LUT4s, contrary to the results of earlier studies nearly a decade ago. We also observed that there are many heterogeneous combinations of small LUTs that do better than either homogeneous LUT3 or LUT4 logic blocks. Our analysis was not as general as the earlier studies and does not cover all LUT-k blocks, especially the larger k values. This is still a fertile research area in the light of the new technology parameters.
The first member of the family of FPGAs based on this architecture has already fully functional silicon and preliminary CAD software to support it. The software (especially the place and route) is not yet fully optimized for the features of this architecture. Despite that, the preliminary results fully indicate that we meet the capacity and performance targets even at this early stage, and we expect to surpass them as the software matures.
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