A scientific study of the problems
of digital engineering for space flight systems,
with a view to their practical solution.
Radiation Characterization, and SEU Mitigation, of the Virtex FPGA for Space-Based Reconfigurable Computing
Earl Fuller2, Michael Caffrey1, Anthony Salazar1, Carl Carmichael3, Joe Fabula3
1 Los Alamos National Laboratory
2 Novus Technologies, Inc.
3 Xilinx, Inc.
Abstract
Orbital remote sensing instruments and systems benefit from high performance, adaptable computing systems. Field programmable SRAM-based gate arrays (FPGAs) are usually the chosen platform for real-time reconfigurable computing. This technology is driven by the commercial sector, so devices intended for the space environment must be adapted from commercial product. Total ionizing dose, heavy ion and proton characterization have been performed on Virtex FPGAs fabricated on epitaxial silicon to evaluate the on-orbit radiation performance expected for this technology. The dominant risk is Single Event Upset (SEU), so upset detection and mitigation schemes have also been tested to validate the improvement in the device upset sensitivity and the system consequence of upsets.
Table of Contents
I. Introduction
II. Technology Considerations
III. Radiation Testing
- Total Ionizing Dose Tolerance
- Heavy Ion Static SEU & SEL Characterization
- Proton- Induced SEU Testing
- Discussion of Upset Modes
IV. Mitigation of Single Event Upsets
- Triple Module Redundancy (TMR)
- Bitstream Repair Techniques
- Dynamic-mode SEU Testing
- Testing Procedure
- Results & Interpretation of Dynamic-mode SEU Testing
V. On-Orbit SEU Rate Estimates
VI. Summary & Conclusions
List of Figures
Figure 1. High dose rate performance. In-situ power supply current monitoring shows an increase in leakage above 80krads(Si).
Figure 2. Low dose rate performance. In this case the increase in leakage current occurs above 90krads(Si) and does not constitute a failure below 100krads(Si).
Figure 3. Static heavy ion bit upset cross-section vs. LET for the Virtex FPGA.
Figure 4. Static proton induced bit upset cross-section vs. proton energy for the Virtex FPGA. Note the identification of outliers in the figure indicating that the configuration control circuit upset mode was observed at the highest energies tested (63MeV).
Figure 5. The FIR filter design without triple modular redundancy (TMR) implemented in the XQVR300 for dynamic proton induced SEU testing.
Figure 6. The same FIR filter with TMR implemented in all blocks of the function. This design uses 3 times the resources of the XQVR300.
Figure 7. Block diagram of the block RAM portion of the Combo test design.
Figure 8. Block diagram of the block configuration logic block (CLB) portion of the Combo test design.
Figure 9. This histogram shows the number of bit upsets detected for each dynamic function failure in proton testing. Often, several configuration bits upset before a hard functional upset occurs.
Figure 10. Scatter plot of the fluence to failure of each of the dynamic designs tested. Note that the FIR design that uses both TMR and bitstream mitigation (PRC) shows the best result at roughly 15x improvement over the basic FIR design. Also plotted for reference is the equivalent total static bit fluence to failure which is derived by the product of bit cross-section and total bits. Clearly not every bit upset will result in a functional failure due to the architectural variables in the device.
Figure 11. Scatter plot of the results of fluence to failure trials of different designs and different operating frequencies. Over the range tested, no frequency variation is evident.
Figure 12. This plot is obtained by calculating the hypothetical sensitive volume of the XQVR300 as the product of all of the bits in the FPGA and the average cross-section from figures 3 and 4 earlier in this text. As demonstrated by the dynamic test data, the expected upset rate should be lower depending on the degree of mitigation employed.
Figure 13. Applying the observed dynamic cross-sections to the upset rate calculations of the device, the maximum benefit observed so far in this work is plotted as the combined benefit of redundancy (TMR) and bitstream partial reconfiguration (PRC).
Conclusions
The results of this radiation characterization program show that the Virtex FPGA meets TID and SEL requirements for many orbital applications. The static-cross section has been measured for both heavy ions and protons by testing the device as though it were an SRAM. LET threshold determined in the heavy ion test proved the part is sensitive to the proton portion of the spectrum. Dynamic testing required a proton accelerator to reduce the time to upset to measurable levels (via the lower proton interaction rate).
The upset risk dominates the radiation considerations for this part. The complexity of this device presents new upset modes and makes radiation testing difficult. Design approaches for upset mitigation provide significant improvement, though more work is necessary to determine the source of the remaining sensitive cross-section. Two dynamic upset signatures have been found, soft errors where a reset is sufficient for recovery, and hard errors that require device reconfiguration. In tests without mitigation, 45% of the failures cannot be attributed to configuration bitstream upsets. It is also shown that, on average, 6.5 bitstream upsets are required for a functional failure for the test designs without mitigation. No measurable dependence on clock rate was found.
The utility of the device for orbital remote sensing data processing will depend on the mission requirements. Device processing performance and survivability are exciting, but more work is needed to find the source of the dynamic cross-section remaining after mitigation.
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