A scientific study of the problems
of digital engineering for space flight systems,
with a view to their practical solution.
Jih-Jong Wang, Brian E. Cronquist, and John E. McGowan
Actel Corporation, Sunnyvale, CA 94086, USA
Richard B. Katz
NASA Goddard Space Flight Center, Greenbelt, MD 20771, USA
Abstract
This paper describes the attributes and goals for a radiation-hard and high-reliability Field Programmable Gate Array (FPGA). The first Qualified Manufacturer List (QML) radiation-hardened antifuse FPGA, RH1280, is characterized. Its total dose and Single Event Effects (SEEs) are tested and the results are reported. Trade-offs and limitations in Single Event Upset (SEU) hardening are also discussed.
Table of Contents
I. Introduction
II. FPGAS In Radiation Environment
III. Actel Antifuse FPGA
IV. RH1280 Characteristics
V. RH1280 Radiation Performance
A. Total Dose Testing
B. Dose Rate Testing
C. SEU Testing
D. SEL Testing
E. SEDR TestingVI. SEU-Hard Design
A. Moderate SEU Hardness
B. Triple Modular Redundancy
C. TMR Circuits with RefreshVII. Summary and Future Trends
List of Figures
Figure 1. TID Test of A1020Z
Figure 2. RH1280 Standby ICC at pre-irradiation (T0), and after series of irradiation and biased anneal.
Figure 3. RH1280 binning circuit delay at pre-irradiation, and after series of irradiation and biased anneal.
Figure 4. SEU data of RH1280 and A1280A FIFOs made of S-, or C-, or MS (modified S)-modules were tested.
Figure 5. RH1280 proton SEU data, which were measured on FIFOs made of S-modules only.
Figure 6. RH1280 S/N 063 Antifuse Rupture
Figure 7. D-type flip-flop implemented with TMR and optional error detector.
Figure 8. Register element with TMR
Figure 9. J-K flip-flop with TMR
List of Tables
Table 1. Actel 1020 devices with total dose tolerance
Table 2. Speed and power of RH1280 and A1280XL
Table 3. The register and I/O delays of a typical design in RH1280 and A1280XL. The min/max values are shown
Conclusion
In summary, a QML/RHA certified antifuse FPGA was developed by implementing an existing commercial design on a rad-hard process. This device is suitable for all aerospace radiation environments, including LEO, GEO, and deep-space. Logic level hardening methodology to combat SEU can be captured in the user software. However, trade offs between SEU hardness and gate density are inevitable.
A sea-of-modules antifuse FPGA architecture, soon to be introduced by Actel, will improve density, speed, and cost. Since a proven design philosophy was implemented, SEL immunity should be preserved. At the same time, the in-operation electric field in its antifuse is one order of magnitude less than in the ONO antifuse. This should eliminate SEDR. Preliminary SEE and total dose data will be published shortly.
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