A scientific study of the problems
of digital engineering for space flight systems,
with a view to their practical solution.
Presented at the 1999 IEEE Nuclear Space Radiation Effects Conference
R. Katz1, J. Wang2, J. McCollum2, and B. Cronquist2
1NASA Goddard Space Flight Center, Greenbelt, MD 20771
2Actel Corporation, Sunnyvale, CA 94086
Abstract
Field programmable gate array (FPGA) devices, heavily used in spacecraft electronics, have grown substantially in size over the past few years, causing designers to work at a higher conceptual level, with computer aided engineering (CAE) tools synthesizing and optimizing the logic from a description. It is shown that the use of commercial-off-the-shelf (COTS) CAE tools can produce unreliable circuit designs when the device is used in a radiation environment and a flip-flop is upset. At a lower level, software can be used to improve the SEU performance of a flip-flop, exploiting the configurable nature of FPGA technology and on-chip delay, parasitic resistive, and capacitive circuit elements.
Table of Contents
I Introduction
II. Impact of CAE Tools
- CAE Optimizations and SoC Issues
- State Machine Encoding and Analysis
- State Machine Recovery
III. Improvement of SEE Performance
IV. Conclusion
List of Figures
Figure 1. Example of CAE tool speed optimization on a portion of a space-flight design. The two circuits are logically equivalent when analyzed with Boolean logic equations with the lower, CAE-optimized circuit, permitting higher device speeds. An SEU analysis shows the addition of a second state variable with an upset resulting in the "optimized" circuit containing a state where Q = QN, violating the system equations and causing a failure.
Figure 2. Two methods of signal distribution. The top version shows a signal distributed to multiple blocks with bufferings driving multiple loads. The bottom version replicates flip-flops, resulting in higher system speeds. Routing delays are significant. Recovery from SEUs with multiple flip-flops are not considered by current computer-aided engineering tools.
Figure 3. A simple one-hot state machine structure. Normal operation has exactly one flip-flop set, all other flip-flops reset. Next state logic equations for each flip-flop depend solely on a single state (flip-flop) and external inputs. Next state equations for binary encoded state machines are dependent on all of the flip-flops in the implementation. This structure is typical of the output of a CAE tool. Note that there are no gates generated for either fault detection or correction. Initialization logic, which sets exactly 1 flip-flop to a '1' is not shown.
Figure 4. Modified one-hot state machine (reset logic omitted) for a 4-state, two-phase, non-overlapping clock generator. A NOR of all flip-flop outputs and the home state being encoded as the zero vector adds robustness. Standard one-hot state machines [Q3 would be tied to the input of the first flip] have 1 flip-flop per state, with exactly one flip-flop set per state, presenting a non-recoverable SEU hazard.
Figure 5. Improvement in SEU performance by exploiting parasitic circuit elements and inserting them into the feedback loop of flip-flops. A mirror topology is used for these Act 1 devices, where each buffer in the feedback loop inverts, as the SEU responsive is not symmetrical The LETTH for this 1.2 µm has improved from ~18 to ~40 MeV-cm2/mg. Data is available from devices with 2.0 µm to 0.25 µm feature sizes.
Figure 6. Comparisons of hardened flip-flops using inverting and non-inverting buffer elements to create latches. These tests indicate that latches with inverting buffer elements had better SEU performance than those with non-inverting elements. Latches with inverting buffers can not be implemented in Act 2 and 3 technologies. 1.2 µm Act 1 technology was used for these experiments.
Figure 7. SEU performance increase as a function of additional delay and parasitic circuit elements in the feedback loop. Data shown is for an Act 2, 1.0 µm device, where a mirror topology is not available. Hard performance can be obtained with equivalent resource usage as TMR with less restrictions on circuit application.
Figure 8. SEU performance increase as a function of flip-flop configuration, feature size, and supply voltage for two prototype devices in SX technology. A) shows the results for 0.6 µm, 3.3 VDC prototypes. B) shows performance of the 0.25 µm, 2.5 VDC devices. 0.35 µm, 3.3 VDC data is not yet available. Performance for hardwired flip-flops (R-Cells) is similar. The performance improvement for routed flip-flops (C-Cell) decreases at the smaller feature size, lower voltage device samples.
Conclusion
CAE software will have an increasing role in the application of FPGAs as the size and complexity of circuitry increases and available development time decreases. Commercial CAE systems and HDLs, used to satisfy these requirements, were not designed for the synthesis of high-reliability/radiation-hardened electronics. Their higher level of abstraction permits faster design cycles but can create SEU hazards for critical applications since the implementation details are not presented to the designer. Careful design, specification, and analysis is needed to design reliable sequencers using an HDL in the SEU environment as opposed to schematic entry, where the designer maintains complete control. In contrast, software, when used at a low level with knowledge of the microcircuit and its characteristics, can be used to improve the SEU response of the hardware, at a cost of additional hardware. This cost may be less than other methods of flip-flop hardening at the circuit design level.
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