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A scientific study of the problems of digital engineering for space flight systems,
with a view to their practical solution.

 

SRAM Based Re-programmable FPGA for Space Applications

J. J. Wang1, Member, IEEE, R. B. Katz2, J. S. Sun1, B. E. Cronquist1, Member, IEEE, J. L. McCollum1, T. M. Speers1, Member, IEEE, and W. C. Plants1

1Actel Corporation, Sunnyvale, California 94086
2NASA Goddard Space Flight Center, Greenbelt, Maryland, 20771

Abstract

An SRAM (static random access memory)-based reprogrammable FPGA (field programmable gate array) is investigated for space applications. A new commercial prototype, named the RS family, was used as an example for the investigation. The device is fabricated in a 0.25µm CMOS technology. Its architecture is reviewed to provide a better understanding of the impact of single event upset (SEU) on the device during operation. The SEU effect of different memories available on the device is evaluated. Heavy ion test data and SPICE simulations are used integrally to extract the threshold LET (linear energy transfer). Together with the saturation cross-section measurement from the layout, a rate prediction is done on each memory type. The SEU in the configuration SRAM is identified as the dominant failure mode and is discussed in detail. The single event transient error in combinational logic is also investigated and simulated by SPICE. SEU mitigation by hardening the memories and employing EDAC (error detection and correction) at the device level are presented. For the configuration SRAM (CSRAM) cell, the trade-off between resistor de-coupling and redundancy hardening techniques are investigated with interesting results. Preliminary heavy ion test data show no sign of SEL (single event latch-up). With regard to ionizing radiation effects, the increase in static leakage current (static ICC) measured indicates a device tolerance of approximately 50 krad(Si).

Table of Contents

I. Introduction
II. Device Technology
III. Device Architecture and SEU

    1. Architecture Overview
    2. Memory Types
    3. CSRAM SEU
    4. USRAM SEU
    5. User FF SEU
    6. Control Logic SEU

IV. SEU in Memories

    1. Heavy Ion Testing Results and SPICE Simulation
    2. SEU Rate Prediction

V. Single Event Transient Errors in Combinational Logic

    1. Mode 1 Single Event Transient
    2. Mode 2 Single Event Transient

VI. SEU Mitigation

    1. Memory Hardening
    2. Device Level Mitigation by EDAC

VII. Single Event Latch-up (SEL)
VIII. Total Dose Effects
IX. Conclusions

List of Figures

Figure 1. The schematics of the CSRAM controlled switch.

Figure 2. Floor plan of a four B16x16 tile (B4) RS device

Figure 3. The logic blocks and routing in B1.

Figure 4. Drive contention due to CSRAM SEU.

Figure 5. Mode 1 single event transient in combinational logic.

Figure 6. Mode 2 single event transient, metastability in CSRAM modifies the data signal.

Figure 7. Mode 2 transient SEU, single event induced metastability in CSRAM controlled MUX.

Figure 8. Resistor hardened SRAM.

Figure 9. Schematic of the DICE SRAM.

Figure 10. ICC of a non-programmed B4 part during Br ion (LET = 37 MeV-cm2/mg) bombardment.

Figure 11. IDS-VGS of a 0.25µm NMOSFET pre- and post- 100krad(Si) irradiation.

Figure 12. Static ICC versus total dose of a 0.25µm B4 device.

List of Tables

Table 1. Key Fabrication parameters.

Table 2. The upset rates of different memory types in GEO environment.

Table 3. Upset rates for resistor hardened SRAMs.

Table 4. Upset rates of DICE SRAM for SSDU process.

Table 5. SSDU process for resistor hardened SRAMs.

Table 6. TID tolerance for different technologies.

Conclusions

For single event effects, the 0.25µm SRAM based reprogrammable FPGA presented in this paper needs to be hardened for space applications. The critical issue is the SEU hardening of the configuration SRAM (CSRAM) to avoid functional failure (or interrupt). CSRAM hardening is particularly difficult because of the constraint of its large population and small size. The traditional methods including resistor and redundancy hardening have their limitations, and the penalties paid for hardening are higher for smaller feature size. At high LET ranges, the hardened CSRAMs will induce single event transient glitches, and may increase the soft error rate of the device. SEL appeared to be not a big issue for this particular device. The data show that it at least has relatively good SEL tolerance (LETth > 74MeV-cm2/mg).

The TID issue is alleviated when feature size shrinks in the sub-micron regime. Several process parameters changed for scaling, such as thinner field oxide, higher well/substrate doping, and lower VCC helped to reduce the TID induced leakage current, and consequently improved the TID tolerance. The present device has TID tolerance of approximately 50 to 100krad(Si).

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Last Revised January 09, 2002
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