A scientific study of the problems
of digital engineering for space flight systems,
with a view to their practical solution.
Presented at the 1999 IEEE NSREC
July, 1999
R. Katz1, J.J. Wang2, R. Reed1, I.
Kleyner3, M. D'Ordine4, J. McCollum2, B. Cronquist2,
and J. Howard5
1NASA Goddard Space Flight Center, Greenbelt, MD 20771
2Actel Corporation, Sunnyvale, CA 94086
3Orbital Sciences Corporation, Greenbelt, MD 20771
4Ball Aerospace and Technologies Corp., Boulder, CO 803014
5Jackson and Tull, Chartered Engineers, Seabrook, MD 20706
Abstract
Architecture and process, combined, significantly affect the hardness of programmable technologies. The effects of high energy ions, ferroelectric memory architectures, and shallow trench isolation are investigated. A detailed single event latchup (SEL) study has been performed.
Table of Contents
I. Introduction
II. Ferroelectric Memories
III. Energy Dependence of Heavy-Ion Induced Single Event Latchup and Dielectric Rupture.
A. Introduction
B. Using the Appropriate Ground Based Radiation Environment
C. SEDR Experimental Setup and Results
D. SEL Experimental Results and DiscussionIV. Shallow Trench Isolation
V. Latchup Issues
VI. Conclusions
List of Figures
Figure 1. FRAM memory cell stores data within a crystalline structure and maintains two stable states, providing non-volatile storage. The ferroelectric film is deposited between electrode plates to form a capacitor [Figure from RAMTRON, Corp.].
Figure 2. Two-transistor, two-capacitor (2T2C) FRAM memory cell. The differential architecture provides each bit with its own reference, eliminating capacitor variance over the die. High density memories, 1 megabit, will likely use a 1T1C cell and a global reference. Reads are destructive [Figure from RAMTRON, Corp.].
Figure 3. Strip chart of FM1608 (research fab) current during heavy ion irradiation. The device lost functionality during the test while the current decreased from it's normal dynamic levels of approximately 6.3 mA to it's quiescent value, near zero. The device recovered functionally and operated normally throughout the latter part of the test. This effect was seen at least three times during the limited testing of this device.
Figure 4. In situ static current measurements of two serial and one parallel FRAM device types. This initial study showed that Rohm (serial) and Ramtron research fab (parallel) devices could withstand moderate doses without significant leakage currents. Post irradiation testing of the FM1608 showed that all devices catastrophically failed. Annealing did not help. In situ functional tests or a step irradiation method are needed for determination of the functional limit. The base CMOS process is not the limiting factor for the FM1608. Only ICC was measured on the serial devices.
Figure 5. Comparison of galactic cosmic ray spectrum between all elements and iron at geostationary orbit behind 100 mils of spherical aluminum shielding. Note that for LETs > 20 Me-cm2/mg the space environment is >65% Iron. The energy per unit mass for iron ions with this LET is < 10 MeV/amu. This shows the importance of performing radiation testing at low and high energy for phenomena exhibiting and energy dependence.
Figure 6. Comparison of critical bias measurements for antifuse rupture at BNL and NSCL. No significant dependence on energy is found and the lower energy BNL ions were the worst-case.
Figure 7. Heavy-ion cross section data taken at BNL and at NSCL on TIC43. Note that BNL data taken at some angle of incidence shows a different LET threshold than that at normal incidence. The NSCL data is normal incidence. The energy dependence of LET threshold is small with lower energy being more conservative. Low number of events limits the analysis of difference in SEL cross section.
Figure 8. Leakage current of STI as a function of total dose exposure. Two device types (both early prototypes) of completely different architectures were tested. Each was built on a 0.25 µm, 2.5 volt STI process. Results are similar to 0.35 µm, 3.3 volt LOCOS process.
Figure 9. One effect of prolonged latchup on an A1020B. Large current jumps were observed on many devices; this run showed that, while the current was decreasing and the part appeared stable, ICC rapidly increased, hitting the current limit of 800 mA programmed for that run.
Figure 10. Distribution of peak latchup currents for the A1020B (MEC). Each label shows the maximum value for its bin. A wide range of latchup currents shows the need for large test sets if a latchup detection and removal circuit is contemplated. DC current shifts from TID exposure and transient current surges from normal operation must be distinguished from latchups with low current values. High latchup currents may blow fuses, trigger overcurrent protections, or place a supply into constant current mode, dropping the voltage, possibly affecting additional circuits and system performance.
List of Tables
Table 1. Ion species used at each facility.
Table 2. SEL Summary for A1020B. A large set of parts from multiple lots were tested, showing a wide range of SEL LETTH and latchup currents. Some latchups were destructive with either higher ICC or functional failure.
Conclusions
This examination of the effects of architecture and process on the radiation hardness of programmable technologies make it clear that this specialized technology class must be analyzed tested carefully, on a case by case basis. Antifuse hardness, having been studied with low energy heavy ions, is seen to have similar critical bias voltages under exposure to high energy ions. Latchup for some programmable designs is a function of the feature size, with the closer structures in the shrunk design leading to a latchup susceptibility. This testing showed no significant difference whether high or low energy ions are used, with the lower energy ions being slightly more conservative. This may be important for failure rate predictions and test strategies, with the lower energy, more cost-effective beams being adequate for testing and qualification. Similar to the proton susceptibility study performed on DRAMs and the FPGA's [7], we see that a small sample set for detailed latchup studies may be inadequate. This is of increased importance if a latchup detection and removal circuit is being designed. Our study of commercial FRAM technologies shows that leakage current, an indicator of damage in typical CMOS digital circuits, can be a poor metric to judge damage to the overall chip, for total dose exposures. Additionally, porting the FRAM device to a new fabrication facility had a significant change in SEL performance, showing the effect of process. This is in direct contrast to the A1020x experiment, where it was shown that design was the key driver, not a change of process. Each of these unique devices must be evaluated and analyzed on a case by case basis. Rules of thumb and "proof by similarity" often do not apply to these technologies.
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