A scientific study of the problems
of digital engineering for space flight systems,
with a view to their practical solution.
Presented at the 1999 MAPLD International Conference
September, 1999
Laurel, MD
I. Kleyner1, R. Katz2 and H. Tiggeler3
1Orbital Sciences Corp.
2NASA/Goddard Space Flight Center
3University of Surrey
Abstract
This paper presents a methodology and a tool set which implements automated generation of moderate-size blocks of customized intellectual property (IP), thus effectively reusing prior work and minimizing the labor intensive, error-prone parts of the design process. Customization of components allows for optimization for smaller area and lower power consumption, which is an important factor given the limitations of resources available in radiation-hardened devices. The effects of variations in HDL coding style on the efficiency of synthesized code for various commercial synthesis tools are also discussed.
Table of Contents
- Introduction
- IP Generation Environment
- Combinational IP Blocks And Coding Styles
- Sequential IP Blocks
- Conclusions
List of Figures
Figure 1. Kompiler IP Generation Flow.
Figure 2. Kompiler User Interface.
Figure 3a. Sine Wave Synthesis Results for Actel Act 3 Target Technology.
Figure 3b. Sine Wave Synthesis Results for Actel SX Target Technology.
Figure 3c. Correlator LUT Synthesis Results for Actel SX Target Technology.
Figure 4. 29KPL154 Generation.
Figure 5. Controller Implementation with 29KPL154 utilizing various levels of customization.
Conclusions
The Kompiler development is still very much a work in progress, as the verification effort for 29KPL154 is under way and additional components are incorporated into Kompiler environment. Indeed, the extensible design of the Kompiler is geared towards continuously adding new components and features, while presenting the user with a consistent, easy-to-use interface.
Nevertheless, the concept of generating small and moderately sized custom-configured blocks of IP using an integrated environment such as Kompiler seems to be proven as a realistic task. It is also quite obvious that at the very least using automated generation of IP blocks shortens the development time and helps avoid simple coding errors. For certain tasks, like generating a large block of combinational logic the manual coding approach is extremely labor-intensive and error-prone, and utilizing Kompiler code-generating capabilities allows for tremendous savings in engineering time and optimization sometimes unattainable with traditional methods. The rapid generation of HDL using different coding styles makes optimization of large logic blocks feasible, practical, and effective.
It was also shown that along with small and simple blocks, more complex and comprehensive cores capable of substantial functionality can be integrated into fully automated IP-generating environment such as Kompiler. The 29KPL154 has the capability to be a cornerstone of SoC implementation using a small processor for a spaceflight application, yet it can be customized to fit in a small, radiation-hardened FPGA.
We have also determined that combining HLL-based software equipped with a simple user interface with VHDL permits a convenient and flexible approach to hardware design. The resulting environment is suitable for implementing components ranging from very simple and universal to more complex and specialized; however, the task of embedding and customizing a component as well as designing a suitable user interface escalates greatly with block’s increasing complexity.
Additionally, it was shown conclusively that various synthesis tools perform identical tasks with various degree of efficiency depending on the style of coding, the specific data content, and the software revision level of the tool.
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