A scientific study of the problems
of digital engineering for space flight systems,
with a view to their practical solution.
Ben Cohen
VhdlCohen Publishing
http://www.vhdlcohen.com/
vhdlcohen@aol.com
Abstract
This paper presents, by example, some of the key features of the front-end processes for specifying the planning of both the implementation and verification (i.e., testbench) of a design to ensure that the implemented design meets its intended requirements and costs.
Table of Contents
1. Introduction
2. When Does Verification Start?
3. Verification Plan
3.1. Tests or Transactions Applied to the Design
3.2. Testbench Environment for the Design-Under-Test
3.3. Verification Language
3.4. Transactions Definition and Sequencing Methods
3.5. Transactions Driving Methods
3.6. Detailed Testbench Architecture (Example)
3.7. Subblock Verification
3.8. Instruction File
3.9. Verifier
3.9.1. Error Detection by Verifier4. Verifier Design
4.1. Issues
4.1.1. Synchronization between UUT and Verifier
4.2. Verifier Design Approach5. Conclusion and Recommendations
List of Figures
Figure 2. Typical Design Processes
Figure 3.6. Testbench Architecture Overview using BFMs and Automatic Verification
Figure 3.7. Subblock Verification Overview using BFMs and Visual Verification
Figure 3.8. Sample Text Command File
Figure 4.1.1. Mismatch between Verifier and UUT because of Lack of Cycle Synchronization
Figure 4.2. High Level View of the Verification Interfaces and Approach
List of Tables
Table 3.1. Feature Extraction and Verification Criteria
Table 3.8. Transaction Instructions used in Files
Table 3.9.1-1. Error Reporting Format and Example
Table 3.9.1-2. List of Errors Reported by Verifier
Table 3.10. Compliance Matrix
Conclusion
The front-end processes for specifying the requirements and the planning of both the implementation and verification of a design are necessary steps to ensure that the implemented design meets its intended goals and costs. To maintain consistency within an organization/company it is important that a common structure for defining and reviewing the requirements and design and verification plan be used. Verification is an intense operation. The concepts of functional verification are language indifferent because it is necessary to apply test transactions and verify that the unit under test is responding as expected. The implementation of transaction based methods for the test vectors promote readability, reuse, and ease the verification process. The design of the verifier for automatic design verification is very critical, and it must be carefully planned. The verifier must operate correctly in a manner that is independent of the internal cycle timing of the design. The verifier model must be readable, easy to use, and must adapt to changes in requirements.
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Last Revised January 09, 2002
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