A scientific study of the problems
of digital engineering for space flight systems,
with a view to their practical solution.
David Williams, Ruth Bishop, Andrew Loyd, Dennis Adams
Northrop Grumman Corporation
Baltimore MD
James Murray, Michael Knoll
Sandia National Laboratories
Albuquerque NM
Abstract
A 32K X 8 radiation tolerant CMOS/SONOS EEPROM is described. The technology is a 1.2 micrometer radiation tolerant CMOS process into which is incorporated an oxidenitride-oxide nonvolatile memory dielectric. This ONO dielectric when used as the gate dielectric of an n channel MOSFET, forms the variable threshold transistor which is the basis for the EEPROM. Charge is stored by tunneling into traps in the nitride, rather than on a floating gate as is done with most EEPROMs. No hot electron effects are used for programming or erase, so programming and erase power dissipation are quite low. Circuit design was done at Sandia National Labs and device fabrication is done by Northrop Grumman Corporation.
Table of Contents
Conclusions
First deliveries of prototype parts were made in the first quarter of 1998. Early characterization data looks positive and efforts are continuing toward qualification and first parts qualified for use in space. Characterization and radiation data are being taken to confirm the preliminary numbers in the table, which are largely based on 8K X 8 data. The intention is to bring this part up to space qualified status, and offer it to the defense and space community as a higher density alternative to the 8K X 8 device. As shown in the figures, total dose hardness looks good. Single event upset and transient radiation data is planned and will be presented at the conference, if available in time. Results are anticipated to be similar to the 8K X 8, since most circuits are the same. The plan is to offer this device in die form, for use in MCMs, as well as in package form.
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