--============================================================================-- -- Design unit : EDAC Testbench (entity and architecture declarations) -- -- File name : edac_tb.vhd -- -- Purpose : Generate and check all possible single and double bit errors. -- -- Note : Leftmost bit no. 0 is the most significant. -- -- Library : EDAC_Lib {recommended} -- -- Author : Sandi Habinc -- European Space Agency (ESA) -- P.O. Box 299 -- NL-2200 AG Noordwijk ZH -- The Netherlands -- -- Contact : mailto:microelectronics@estec.esa.int -- http://www.estec.esa.int/microelectronics -- -- Copyright (C): European Space Agency (ESA) 2000. -- This source code is free software; you can redistribute it -- and/or modify it under the terms of the GNU Lesser General -- Public License as published by the Free Software Foundation; -- either version 2 of the License, or (at your option) any -- later version. For full details of the license see file -- http://www.estec.esa.int/microelectronics/copying.lgpl -- -- It is recommended that any use of this VHDL source code is -- reported to the European Space Agency. It is also recommended -- that any use of the VHDL source code properly acknowledges the -- European Space Agency as originator. -- -- Disclaimer : All information is provided "as is", there is no warranty that -- the information is correct or suitable for any purpose, -- neither implicit nor explicit. This information does not -- necessarily reflect the policy of the European Space Agency. -------------------------------------------------------------------------------- -- Version Author Date Changes -- 0.1 ESA 15 Jun 00 New testbench -- 0.2 ESA 10 Jul 00 Adapted to codec with separate encoder/decoder -- 0.4 ESA 1 Dec 00 Added support for 4/16/24/32/40/48/64 bit EDACs -------------------------------------------------------------------------------- entity EDAC_TestBench is generic( EDACType: Natural range 0 to 10 := 0; -- EDAC type selection LongSuite: Natural range 0 to 1 := 0; -- Long test suite ShortData: Natural range 0 to 1 := 0); -- Shortened data test end EDAC_TestBench; --============================================================================-- library IEEE; use IEEE.Std_Logic_1164.all; use IEEE.Std_Logic_Arith.all; use IEEE.Std_Logic_TextIO.all; library Std; use Std.TextIO.all; library Work; use Work.EDAC.all; architecture Behavioural of EDAC_TestBench is ----------------------------------------------------------------------------- -- Calculate data width ----------------------------------------------------------------------------- function DataWidth return Natural is begin if EDACType=0 then report "-- 4 bit Hamming coded EDAC --"; return 4; elsif EDACType=1 then report "-- 8 bit Hamming coded EDAC --"; return 8; elsif EDACType=2 then report "-- 8 bit quasi-cyclic coded EDAC --"; return 8; elsif EDACType=3 then report "-- 16 bit Hamming coded EDAC --"; return 16; elsif EDACType=4 then report "-- 16 bit strong Hamming coded EDAC --"; return 16; elsif EDACType=5 then report "-- 24 bit Hamming coded EDAC --"; return 24; elsif EDACType=6 then report "-- 32 bit Hamming coded EDAC --"; return 32; elsif EDACType=7 then report "-- 32 bit strong Hamming coded EDAC --"; return 32; elsif EDACType=8 then report "-- 40 bit Hamming coded EDAC --"; return 40; elsif EDACType=9 then report "-- 48 bit Hamming coded EDAC --"; return 48; elsif EDACType=10 then report "-- 64 bit Hamming coded EDAC --"; return 64; else report "Unsupported EDAC type" severity Failure; return 64; end if; end DataWidth; ----------------------------------------------------------------------------- -- Calculate check width ----------------------------------------------------------------------------- function CheckWidth return Natural is begin if EDACType=0 then return 4; elsif EDACType=1 then return 8; elsif EDACType=2 then return 8; elsif EDACType=3 then return 6; elsif EDACType=4 then return 8; elsif EDACType=5 then return 7; elsif EDACType=6 then return 7; elsif EDACType=7 then return 8; elsif EDACType=8 then return 7; elsif EDACType=9 then return 7; elsif EDACType=10 then return 8; else return 8; end if; end CheckWidth; ----------------------------------------------------------------------------- -- Set data and check widths ----------------------------------------------------------------------------- constant DWidth: Natural := DataWidth; constant CWidth: Natural := CheckWidth; subtype DRange is Natural range 0 to DWidth-1; ----------------------------------------------------------------------------- -- Set data range, full range or shortened to only all zero value ----------------------------------------------------------------------------- constant DataRange: Natural := (2**DWidth-1) * (1-ShortData); ----------------------------------------------------------------------------- -- Local signals of generic size supporting up to 64 bit data and 8 check bit ----------------------------------------------------------------------------- signal EDACDout: Word64; -- Output data word signal EDACPout: Word8; -- Output check bits signal EDACDin: Word64; -- Input data word signal EDACPin: Word8; -- Input check bits signal EDACCorr: Word64; -- Corrected data signal EDACsErr: Std_ULogic; -- Single error signal EDACdErr: Std_ULogic; -- Double error signal EDACuErr: Std_ULogic; -- Uncorrectable error begin ----------------------------------------------------------------------------- -- Select EDAC type ----------------------------------------------------------------------------- EDAC0: if EDACType=0 generate EDAC4Hamming( DataOut => EDACDout(0 to 3), CheckOut => EDACPout(0 to 3), DataIn => EDACDin(0 to 3), CheckIn => EDACPin(0 to 3), DataCorr => EDACCorr(0 to 3), SingleErr => EDACsErr, DoubleErr => EDACdErr, MultipleErr => EDACuErr); end generate; EDAC1: if EDACType=1 generate EDAC8Hamming( DataOut => EDACDout(0 to 7), CheckOut => EDACPout, DataIn => EDACDin(0 to 7), CheckIn => EDACPin, DataCorr => EDACCorr(0 to 7), SingleErr => EDACsErr, DoubleErr => EDACdErr, MultipleErr => EDACuErr); end generate; EDAC2: if EDACType=2 generate EDAC8Cyclic( DataOut => EDACDout(0 to 7), CheckOut => EDACPout, DataIn => EDACDin(0 to 7), CheckIn => EDACPin, DataCorr => EDACCorr(0 to 7), SingleErr => EDACsErr, DoubleErr => EDACdErr, MultipleErr => EDACuErr); end generate; EDAC3: if EDACType=3 generate EDAC16Hamming( DataOut => EDACDout(0 to 15), CheckOut => EDACPout, DataIn => EDACDin(0 to 15), CheckIn => EDACPin, DataCorr => EDACCorr(0 to 15), SingleErr => EDACsErr, DoubleErr => EDACdErr, MultipleErr => EDACuErr); end generate; EDAC4: if EDACType=4 generate EDAC16Strong( DataOut => EDACDout(0 to 15), CheckOut => EDACPout, DataIn => EDACDin(0 to 15), CheckIn => EDACPin, DataCorr => EDACCorr(0 to 15), SingleErr => EDACsErr, DoubleErr => EDACdErr, MultipleErr => EDACuErr); end generate; EDAC5: if EDACType=5 generate EDAC24Hamming( DataOut => EDACDout(0 to 23), CheckOut => EDACPout, DataIn => EDACDin(0 to 23), CheckIn => EDACPin, DataCorr => EDACCorr(0 to 23), SingleErr => EDACsErr, DoubleErr => EDACdErr, MultipleErr => EDACuErr); end generate; EDAC6: if EDACType=6 generate EDAC32Hamming( DataOut => EDACDout(0 to 31), CheckOut => EDACPout, DataIn => EDACDin(0 to 31), CheckIn => EDACPin, DataCorr => EDACCorr(0 to 31), SingleErr => EDACsErr, DoubleErr => EDACdErr, MultipleErr => EDACuErr); end generate; EDAC7: if EDACType=7 generate EDAC32Strong( DataOut => EDACDout(0 to 31), CheckOut => EDACPout, DataIn => EDACDin(0 to 31), CheckIn => EDACPin, DataCorr => EDACCorr(0 to 31), SingleErr => EDACsErr, DoubleErr => EDACdErr, MultipleErr => EDACuErr); end generate; EDAC8: if EDACType=8 generate EDAC40Hamming( DataOut => EDACDout(0 to 39), CheckOut => EDACPout, DataIn => EDACDin(0 to 39), CheckIn => EDACPin, DataCorr => EDACCorr(0 to 39), SingleErr => EDACsErr, DoubleErr => EDACdErr, MultipleErr => EDACuErr); end generate; EDAC9: if EDACType=9 generate EDAC48Hamming( DataOut => EDACDout(0 to 47), CheckOut => EDACPout, DataIn => EDACDin(0 to 47), CheckIn => EDACPin, DataCorr => EDACCorr(0 to 47), SingleErr => EDACsErr, DoubleErr => EDACdErr, MultipleErr => EDACuErr); end generate; EDAC10: if EDACType=10 generate EDAC64Hamming( DataOut => EDACDout(0 to 63), CheckOut => EDACPout, DataIn => EDACDin(0 to 63), CheckIn => EDACPin, DataCorr => EDACCorr(0 to 63), SingleErr => EDACsErr, DoubleErr => EDACdErr, MultipleErr => EDACuErr); end generate; ----------------------------------------------------------------------------- -- Generate and check all possible single and double bit errors. ----------------------------------------------------------------------------- Main: process variable Data: Std_Logic_Vector(0 to DWidth-1); variable CountSErr, CountDErr, CountUErr: Natural := 0; variable CountTotal, CountNoErr, CountDataErr: Natural := 0; variable L: Line; begin -------------------------------------------------------------------------- -- -------------------------------------------------------------------------- if ShortData=0 then Write(L, String'("-- Only a single data value used in test --")); WriteLine(Output,L); else Write(L, String'("-- All possible data values used in test --")); WriteLine(Output,L); end if; if LongSuite=0 then Write(L, String'("-- Short test suite --")); WriteLine(Output,L); else Write(L, String'("-- Long test suite -- ")); WriteLine(Output,L); end if; -------------------------------------------------------------------------- -- -------------------------------------------------------------------------- Write(L, String'("Test without bit errors")); WriteLine(Output,L); CountSErr := 0; CountDErr := 0; CountUErr := 0; CountTotal := 0; CountNoErr := 0; CountDataErr := 0; for i in 0 to DataRange loop Data := Std_Logic_Vector(Conv_UnSigned(i, DWidth)); EDACDout(DRange) <= Data; EDACDin(DRange) <= Data; wait for 1 ns; EDACPin <= EDACPout; wait for 99 ns; CountTotal := CountTotal+1; if EDACsErr='1' then CountSErr := CountSErr +1; end if; if EDACdErr='1' then CountDErr := CountDErr +1; end if; if EDACuErr='1' then CountUErr := CountUErr +1; end if; if EDACsErr='0' and EDACdErr='0' and EDACuErr='0' then CountNoErr := CountNoErr +1; end if; if EDACCorr(DRange) /= Data then CountDataErr := CountDataErr +1; end if; end loop; assert CountTotal=CountNoErr report "Not an optimal result!"; Write(L, String'("Total: ")); Write(L, CountTotal, Right, 15); WriteLine(Output, L); Write(L, String'("No error: ")); Write(L, CountNoErr, Right, 15); WriteLine(Output, L); Write(L, String'("Single: ")); Write(L, CountSErr, Right, 15); WriteLine(Output, L); Write(L, String'("Double: ")); Write(L, CountDErr, Right, 15); WriteLine(Output, L); Write(L, String'("Uncorrectable: ")); Write(L, CountUErr, Right, 15); WriteLine(Output, L); Write(L, String'("Data error: ")); Write(L, CountDataErr, Right, 15); WriteLine(Output, L); WriteLine(Output, L); -------------------------------------------------------------------------- -- -------------------------------------------------------------------------- Write(L, String'("Test single bit errors in data only")); WriteLine(Output,L); CountSErr := 0; CountDErr := 0; CountUErr := 0; CountTotal := 0; CountNoErr := 0; CountDataErr := 0; for i in 0 to DataRange loop for j in 0 to DWidth-1 loop Data := Std_Logic_Vector(Conv_UnSigned(i, DWidth)); EDACDout(DRange) <= Data; EDACDin(DRange) <= Data; wait for 1 ns; EDACPin <= EDACPout; EDACDin(j) <= not Data(j); wait for 99 ns; CountTotal := CountTotal+1; if EDACsErr='1' then CountSErr := CountSErr +1; end if; if EDACdErr='1' then CountDErr := CountDErr +1; end if; if EDACuErr='1' then CountUErr := CountUErr +1; end if; if EDACsErr='0' and EDACdErr='0' and EDACuErr='0' then CountNoErr := CountNoErr +1; end if; if EDACCorr(DRange) /= Data then CountDataErr := CountDataErr +1; end if; end loop; end loop; assert CountTotal=CountSErr report "Not an optimal result!"; Write(L, String'("Total: ")); Write(L, CountTotal, Right, 15); WriteLine(Output, L); Write(L, String'("No error: ")); Write(L, CountNoErr, Right, 15); WriteLine(Output, L); Write(L, String'("Single: ")); Write(L, CountSErr, Right, 15); WriteLine(Output, L); Write(L, String'("Double: ")); Write(L, CountDErr, Right, 15); WriteLine(Output, L); Write(L, String'("Uncorrectable: ")); Write(L, CountUErr, Right, 15); WriteLine(Output, L); Write(L, String'("Data error: ")); Write(L, CountDataErr, Right, 15); WriteLine(Output, L); WriteLine(Output, L); -------------------------------------------------------------------------- -- -------------------------------------------------------------------------- Write(L, String'("Test single bit errors in check bits only")); WriteLine(Output,L); CountSErr := 0; CountDErr := 0; CountUErr := 0; CountTotal := 0; CountNoErr := 0; CountDataErr := 0; for i in 0 to DataRange loop for j in 0 to CWidth-1 loop Data := Std_Logic_Vector(Conv_UnSigned(i, DWidth)); EDACDout(DRange) <= Data; EDACDin(DRange) <= Data; wait for 1 ns; EDACPin <= EDACPout; EDACPin(j) <= not EDACPout(j); wait for 99 ns; CountTotal := CountTotal+1; if EDACsErr='1' then CountSErr := CountSErr +1; end if; if EDACdErr='1' then CountDErr := CountDErr +1; end if; if EDACuErr='1' then CountUErr := CountUErr +1; end if; if EDACsErr='0' and EDACdErr='0' and EDACuErr='0' then CountNoErr := CountNoErr +1; end if; if EDACCorr(DRange) /= Data then CountDataErr := CountDataErr +1; end if; end loop; end loop; assert CountTotal=CountSErr report "Not an optimal result!"; Write(L, String'("Total: ")); Write(L, CountTotal, Right, 15); WriteLine(Output, L); Write(L, String'("No error: ")); Write(L, CountNoErr, Right, 15); WriteLine(Output, L); Write(L, String'("Single: ")); Write(L, CountSErr, Right, 15); WriteLine(Output, L); Write(L, String'("Double: ")); Write(L, CountDErr, Right, 15); WriteLine(Output, L); Write(L, String'("Uncorrectable: ")); Write(L, CountUErr, Right, 15); WriteLine(Output, L); Write(L, String'("Data error: ")); Write(L, CountDataErr, Right, 15); WriteLine(Output, L); WriteLine(Output, L); -------------------------------------------------------------------------- -- -------------------------------------------------------------------------- Write(L, String'("Test double bit errors in data and/or check bits")); WriteLine(Output,L); CountSErr := 0; CountDErr := 0; CountUErr := 0; CountTotal := 0; CountNoErr := 0; CountDataErr := 0; for i in 0 to DataRange loop for j in 0 to DWidth+CWidth-2 loop for k in j+1 to DWidth+CWidth-1 loop Data := Std_Logic_Vector(Conv_UnSigned(i, DWidth)); EDACDout(DRange) <= Data; EDACDin(DRange) <= Data; wait for 1 ns; EDACPin <= EDACPout; if j > DWidth-1 then EDACPin(j-DWidth) <= not EDACPout(j-DWidth); else EDACDin(j) <= not Data(j); end if; if k > DWidth-1 then EDACPin(k-DWidth) <= not EDACPout(k-DWidth); else EDACDin(k) <= not Data(k); end if; wait for 99 ns; CountTotal := CountTotal+1; if EDACsErr='1' then CountSErr := CountSErr +1; end if; if EDACdErr='1' then CountDErr := CountDErr +1; end if; if EDACuErr='1' then CountUErr := CountUErr +1; end if; if EDACsErr='0' and EDACdErr='0' and EDACuErr='0' then CountNoErr := CountNoErr +1; end if; if EDACCorr(DRange) /= Data then CountDataErr := CountDataErr +1; end if; end loop; end loop; end loop; Write(L, String'("Total: ")); Write(L, CountTotal, Right, 15); WriteLine(Output, L); Write(L, String'("No error: ")); Write(L, CountNoErr, Right, 15); WriteLine(Output, L); Write(L, String'("Single: ")); Write(L, CountSErr, Right, 15); WriteLine(Output, L); Write(L, String'("Double: ")); Write(L, CountDErr, Right, 15); WriteLine(Output, L); Write(L, String'("Uncorrectable: ")); Write(L, CountUErr, Right, 15); WriteLine(Output, L); Write(L, String'("Data error: ")); Write(L, CountDataErr, Right, 15); WriteLine(Output, L); WriteLine(Output, L); -------------------------------------------------------------------------- -- -------------------------------------------------------------------------- assert LongSuite=1 report "End of Short Test" severity Failure; -------------------------------------------------------------------------- -- -------------------------------------------------------------------------- Write(L, String'("Test double bit errors in data only")); WriteLine(Output,L); CountSErr := 0; CountDErr := 0; CountUErr := 0; CountTotal := 0; CountNoErr := 0; CountDataErr := 0; for i in 0 to DataRange loop for j in 0 to DWidth-2 loop for k in j+1 to DWidth-1 loop Data := Std_Logic_Vector(Conv_UnSigned(i, DWidth)); EDACDout(DRange) <= Data; EDACDin(DRange) <= Data; wait for 1 ns; EDACPin <= EDACPout; EDACDin(j) <= not Data(j); EDACDin(k) <= not Data(k); wait for 99 ns; CountTotal := CountTotal+1; if EDACsErr='1' then CountSErr := CountSErr +1; end if; if EDACdErr='1' then CountDErr := CountDErr +1; end if; if EDACuErr='1' then CountUErr := CountUErr +1; end if; if EDACsErr='0' and EDACdErr='0' and EDACuErr='0' then CountNoErr := CountNoErr +1; end if; if EDACCorr(DRange) /= Data then CountDataErr := CountDataErr +1; end if; end loop; end loop; end loop; Write(L, String'("Total: ")); Write(L, CountTotal, Right, 15); WriteLine(Output, L); Write(L, String'("No error: ")); Write(L, CountNoErr, Right, 15); WriteLine(Output, L); Write(L, String'("Single: ")); Write(L, CountSErr, Right, 15); WriteLine(Output, L); Write(L, String'("Double: ")); Write(L, CountDErr, Right, 15); WriteLine(Output, L); Write(L, String'("Uncorrectable: ")); Write(L, CountUErr, Right, 15); WriteLine(Output, L); Write(L, String'("Data error: ")); Write(L, CountDataErr, Right, 15); WriteLine(Output, L); WriteLine(Output, L); -------------------------------------------------------------------------- -- -------------------------------------------------------------------------- Write(L, String'("Test double bit errors in check bits only")); WriteLine(Output,L); CountSErr := 0; CountDErr := 0; CountUErr := 0; CountTotal := 0; CountNoErr := 0; CountDataErr := 0; for i in 0 to DataRange loop for j in 0 to CWidth-1 loop for k in j+1 to CWidth-1 loop Data := Std_Logic_Vector(Conv_UnSigned(i, DWidth)); EDACDout(DRange) <= Data; EDACDin(DRange) <= Data; wait for 1 ns; EDACPin <= EDACPout; EDACPin(j) <= not EDACPout(j); EDACPin(k) <= not EDACPout(k); wait for 99 ns; CountTotal := CountTotal+1; if EDACsErr='1' then CountSErr := CountSErr +1; end if; if EDACdErr='1' then CountDErr := CountDErr +1; end if; if EDACuErr='1' then CountUErr := CountUErr +1; end if; if EDACsErr='0' and EDACdErr='0' and EDACuErr='0' then CountNoErr := CountNoErr +1; end if; if EDACCorr(DRange) /= Data then CountDataErr := CountDataErr +1; end if; end loop; end loop; end loop; Write(L, String'("Total: ")); Write(L, CountTotal, Right, 15); WriteLine(Output, L); Write(L, String'("No error: ")); Write(L, CountNoErr, Right, 15); WriteLine(Output, L); Write(L, String'("Single: ")); Write(L, CountSErr, Right, 15); WriteLine(Output, L); Write(L, String'("Double: ")); Write(L, CountDErr, Right, 15); WriteLine(Output, L); Write(L, String'("Uncorrectable: ")); Write(L, CountUErr, Right, 15); WriteLine(Output, L); Write(L, String'("Data error: ")); Write(L, CountDataErr, Right, 15); WriteLine(Output, L); WriteLine(Output, L); -------------------------------------------------------------------------- -- -------------------------------------------------------------------------- Write(L, String'("Test one single bit error in data, together with one")); Write(L, String'(" single bit error in check bits")); WriteLine(Output,L); CountSErr := 0; CountDErr := 0; CountUErr := 0; CountTotal := 0; CountNoErr := 0; CountDataErr := 0; for i in 0 to DataRange loop for j in 0 to DWidth-1 loop for k in 0 to CWidth-1 loop Data := Std_Logic_Vector(Conv_UnSigned(i, DWidth)); EDACDout(DRange) <= Data; EDACDin(DRange) <= Data; wait for 1 ns; EDACPin <= EDACPout; EDACDin(j) <= not Data(j); EDACPin(k) <= not EDACPout(k); wait for 99 ns; CountTotal := CountTotal+1; if EDACsErr='1' then CountSErr := CountSErr +1; end if; if EDACdErr='1' then CountDErr := CountDErr +1; end if; if EDACuErr='1' then CountUErr := CountUErr +1; end if; if EDACsErr='0' and EDACdErr='0' and EDACuErr='0' then CountNoErr := CountNoErr +1; end if; if EDACCorr(DRange) /= Data then CountDataErr := CountDataErr +1; end if; end loop; end loop; end loop; Write(L, String'("Total: ")); Write(L, CountTotal, Right, 15); WriteLine(Output, L); Write(L, String'("No error: ")); Write(L, CountNoErr, Right, 15); WriteLine(Output, L); Write(L, String'("Single: ")); Write(L, CountSErr, Right, 15); WriteLine(Output, L); Write(L, String'("Double: ")); Write(L, CountDErr, Right, 15); WriteLine(Output, L); Write(L, String'("Uncorrectable: ")); Write(L, CountUErr, Right, 15); WriteLine(Output, L); Write(L, String'("Data error: ")); Write(L, CountDataErr, Right, 15); WriteLine(Output, L); WriteLine(Output, L); -------------------------------------------------------------------------- -- -------------------------------------------------------------------------- Write(L, String'("Test tripple bit errors in data and/or check bits")); WriteLine(Output,L); CountSErr := 0; CountDErr := 0; CountUErr := 0; CountTotal := 0; CountNoErr := 0; CountDataErr := 0; for i in 0 to DataRange loop for j in 0 to DWidth+CWidth-3 loop for k in j+1 to DWidth+CWidth-2 loop for l in k+1 to DWidth+CWidth-1 loop Data := Std_Logic_Vector(Conv_UnSigned(i, DWidth)); EDACDout(DRange) <= Data; EDACDin(DRange) <= Data; wait for 1 ns; EDACPin <= EDACPout; if j > DWidth-1 then EDACPin(j-DWidth) <= not EDACPout(j-DWidth); else EDACDin(j) <= not Data(j); end if; if k > DWidth-1 then EDACPin(k-DWidth) <= not EDACPout(k-DWidth); else EDACDin(k) <= not Data(k); end if; if l > DWidth-1 then EDACPin(l-DWidth) <= not EDACPout(l-DWidth); else EDACDin(l) <= not Data(l); end if; wait for 99 ns; CountTotal := CountTotal+1; if EDACsErr='1' then CountSErr := CountSErr +1; end if; if EDACdErr='1' then CountDErr := CountDErr +1; end if; if EDACuErr='1' then CountUErr := CountUErr +1; end if; if EDACsErr='0' and EDACdErr='0' and EDACuErr='0' then CountNoErr := CountNoErr +1; end if; if EDACCorr(DRange) /= Data then CountDataErr := CountDataErr +1; end if; end loop; end loop; end loop; end loop; Write(L, String'("Total: ")); Write(L, CountTotal, Right, 15); WriteLine(Output, L); Write(L, String'("No error: ")); Write(L, CountNoErr, Right, 15); WriteLine(Output, L); Write(L, String'("Single: ")); Write(L, CountSErr, Right, 15); WriteLine(Output, L); Write(L, String'("Double: ")); Write(L, CountDErr, Right, 15); WriteLine(Output, L); Write(L, String'("Uncorrectable: ")); Write(L, CountUErr, Right, 15); WriteLine(Output, L); Write(L, String'("Data error: ")); Write(L, CountDataErr, Right, 15); WriteLine(Output, L); WriteLine(Output, L); -------------------------------------------------------------------------- -- -------------------------------------------------------------------------- Write(L, String'("Test nibble errors in data only")); WriteLine(Output,L); CountSErr := 0; CountDErr := 0; CountUErr := 0; CountTotal := 0; CountNoErr := 0; CountDataErr := 0; for i in 0 to DataRange loop for j in 0 to (DWidth/4)-1 loop Data := Std_Logic_Vector(Conv_UnSigned(i, DWidth)); EDACDout(DRange) <= Data; EDACDin(DRange) <= Data; wait for 1 ns; EDACPin <= EDACPout; EDACDin(j*4) <= not Data(j*4); EDACDin(j*4+1) <= not Data(j*4+1); EDACDin(j*4+2) <= not Data(j*4+2); EDACDin(j*4+3) <= not Data(j*4+3); wait for 99 ns; CountTotal := CountTotal+1; if EDACsErr='1' then CountSErr := CountSErr +1; end if; if EDACdErr='1' then CountDErr := CountDErr +1; end if; if EDACuErr='1' then CountUErr := CountUErr +1; end if; if EDACsErr='0' and EDACdErr='0' and EDACuErr='0' then CountNoErr := CountNoErr +1; end if; if EDACCorr(DRange) /= Data then CountDataErr := CountDataErr +1; end if; end loop; end loop; Write(L, String'("Total: ")); Write(L, CountTotal, Right, 15); WriteLine(Output, L); Write(L, String'("No error: ")); Write(L, CountNoErr, Right, 15); WriteLine(Output, L); Write(L, String'("Single: ")); Write(L, CountSErr, Right, 15); WriteLine(Output, L); Write(L, String'("Double: ")); Write(L, CountDErr, Right, 15); WriteLine(Output, L); Write(L, String'("Uncorrectable: ")); Write(L, CountUErr, Right, 15); WriteLine(Output, L); Write(L, String'("Data error: ")); Write(L, CountDataErr, Right, 15); WriteLine(Output, L); WriteLine(Output, L); -------------------------------------------------------------------------- -- -------------------------------------------------------------------------- Write(L, String'("Test byte errors in data only")); WriteLine(Output,L); CountSErr := 0; CountDErr := 0; CountUErr := 0; CountTotal := 0; CountNoErr := 0; CountDataErr := 0; for i in 0 to DataRange loop for j in 0 to (DWidth/8)-1 loop Data := Std_Logic_Vector(Conv_UnSigned(i, DWidth)); EDACDout(DRange) <= Data; EDACDin(DRange) <= Data; wait for 1 ns; EDACPin <= EDACPout; EDACDin(j*8) <= not Data(j*8); EDACDin(j*8+1) <= not Data(j*8+1); EDACDin(j*8+2) <= not Data(j*8+2); EDACDin(j*8+3) <= not Data(j*8+3); EDACDin(j*8+4) <= not Data(j*8+4); EDACDin(j*8+5) <= not Data(j*8+5); EDACDin(j*8+6) <= not Data(j*8+6); EDACDin(j*8+7) <= not Data(j*8+7); wait for 99 ns; CountTotal := CountTotal+1; if EDACsErr='1' then CountSErr := CountSErr +1; end if; if EDACdErr='1' then CountDErr := CountDErr +1; end if; if EDACuErr='1' then CountUErr := CountUErr +1; end if; if EDACsErr='0' and EDACdErr='0' and EDACuErr='0' then CountNoErr := CountNoErr +1; end if; if EDACCorr(DRange) /= Data then CountDataErr := CountDataErr +1; end if; end loop; end loop; Write(L, String'("Total: ")); Write(L, CountTotal, Right, 15); WriteLine(Output, L); Write(L, String'("No error: ")); Write(L, CountNoErr, Right, 15); WriteLine(Output, L); Write(L, String'("Single: ")); Write(L, CountSErr, Right, 15); WriteLine(Output, L); Write(L, String'("Double: ")); Write(L, CountDErr, Right, 15); WriteLine(Output, L); Write(L, String'("Uncorrectable: ")); Write(L, CountUErr, Right, 15); WriteLine(Output, L); Write(L, String'("Data error: ")); Write(L, CountDataErr, Right, 15); WriteLine(Output, L); WriteLine(Output, L); -------------------------------------------------------------------------- -- -------------------------------------------------------------------------- assert False report "End of Long Test" severity Failure; wait; end process Main; end Behavioural; --===========================================================--