NASA Office of Logic Design

NASA Office of Logic Design

A scientific study of the problems of digital engineering for space flight systems,
with a view to their practical solution.

Briefing on Achronix Technology: High-Speed and Extreme Environment FPGAs and ASICs

On Tuesday November 15, 2005, a briefing Achronix' technology on high-speed and extreme environment FPGAs and ASICs will be given at the NASA Goddard Space Flight Center in Greenbelt, MD.  The briefing will be from 10 am to 12 noon in the Building 11 AETD conference room (S203A).

All attendees should complete the registration form below and observe the following dates.  On-site NASA personnel should also register to aid in event planning and notification of any logistical changes.

Recording of this meeting will not be permitted.  Meeting notes will be distributed via http://klabs.org.

Regards,

-- rk

Presentation Material

References and Additional Reading


Fault Tolerant Asynchronous Adder through Dynamic Self-reconfiguration

Song Peng and Rajit Manohar

 Abstract
This paper presents a systematic method for the design of a reconfigurable self-healing asynchronous adder. We propose a graph-based model for the design of a fault-tolerant linear array with external inputs and outputs with a minimum number of spare resources. A K-fault-tolerant asynchronous adder design is presented based on this analysis, together with the necessary support logic for dynamic self-reconfiguration. Experimental evaluations show that our method incurs both low hardware cost and small performance overhead compared to traditional approaches to fault-tolerance.


Efficient Failure Detection in Pipelined Asynchronous Circuits

Song Peng and Rajit Manohar

 Abstract
This paper presents an efficient concurrent failure detection method for pipelined asynchronous circuits. We first validate permanent and transient fault modeling in clockless systems. By augmenting the rails to each data channel and adding extra logic to each circuit module, we make pipelined asynchronous circuits achieve fail-stop with respect to hard or soft errors. The experimental evaluations show this method incurs both reasonable hardware cost and low performance overhead.


Fault Detection and Isolation Techniques for Quasi Delay-Insensitive

Christopher LaFrieda and Rajit Manohar

 Abstract
This paper presents a novel circuit fault detection and isolation technique for quasi delay-insensitive asynchronous circuits. We achieve fault isolation by a combination of physical layout and circuit techniques. The asynchronous nature of quasi delay-insensitive circuits combined with layout techniques makes the design tolerant to delay faults. Circuit techniques are used to make sections of the design robust to non-delay faults. The combination of these is a asynchronous defect- tolerant circuit where a large class of faults are tolerated, and the remaining faults can be both detected easily and isolated to a small region of the design.

Logistics

Registration  Form for November 15, 2005, Briefing

1. Registration Type
2. First Name
3. Last Name
4. Your E-mail
5. Telephone Number
6. Company Name
7. Citizenship REMEMBER TO FILL THIS FIELD OUT

Comments, notes, and additional information.

Home
Last Revised: November 17, 2005
Digital Engineering Institute
Web Grunt: Richard Katz
NACA Seal