EDUCATION:
B.S.E.E. 1982 State University of New York at Stony Brook
- Majors: Computer Science; Applied Mathematics and Statistics
- Minor: Mathematics
M.S.E.E. 1983 State University of New York at Stony Brook, EE: Computer Engineering and Digital Systems.
RESEARCH INTERESTS:
Design of high-reliability circuits. Use of programmable elements and devices in space-flight applications. High-performance microelectronics and signal processing applications.
EXPERIENCE:
1991-present NASA Goddard Space Flight Center. Head, Office of Logic Design. 1989-91 ST Systems, Corp. (NASA/GSFC Contractor) 1988-89 Hewlett-Packard Corporation 1984-88 Jet Propulsion Laboratory/California Institute of Technology 1982-83 Research and Teaching Assistant, State University of New York at Stony Brook 1981, 83 Summer Intern, McDonnell-Douglas Automation Co. Flight test 1982 Summer Intern, General Instrument Corp. Minicomputer and radar simulator.
PUBLICATIONS and PRESENTATIONS (many of the papers followed conference presentations):
Short Courses/Seminars
Pyrotechnic Initiators, Applications, and Lessons Learned, June 7, 2005
Memory Design for Spaceborne Computers, April, 2005
- A series of independent reviews, briefings, and seminars on Actel FPGA Reliability
- "Design Seminar on Actel SX-A and RTSX-S Programmed Antifuses," NASA Goddard Space Flight Center, Tuesday, April 13, 2004.
- Logic Design: Clocking, Timing Analysis, Finite State Machines, and Verification, 2002 MAPLD International Conference, Laurel, MD.
- Programmable Logic in the Radiation Environment, 2002 MAPLD International Conference, Laurel, MD.
- SDRAM Technology: An Introduction to the Use of the Technology in the High-Reliability, Spaceflight Environment, NASA Goddard Space Flight Center, July 2002.
- Fundamentals of Digital Engineering: Digital Logic, NASA Goddard Space Flight Center, May 2001.
- Programmable Logic Devices and Architectures, NASA Goddard Space Flight Center, March 2001; Longer version given at the 2001 MAPLD International Conference, Laurel, MD.
- Programmable Logic in the Space Environment and Advanced Design Techniques, NASA Goddard Space Flight Center, June 2001.
- Advanced Design: Designing for Reliability, NASA Marshall Space Flight Center, June 2001; Longer version given at the 2001 MAPLD International Conference, Laurel, MD.
Conferences, Invited Talks, Papers, Columns, Reports, and Other Publications
"Design of Memory Systems for Spaceborne Computers," presented at the Flight Software Workshop 2007 (FSW-07) November 5-6, 2007, Laurel, MD.
"Engineering Aspects of the Lunar Orbiter Laser Altimeter (LOLA) Digital Unit Design," seminar held at the NASA Goddard Space Flight Center, October 17, 2007.
"Common Mode Failures in Safety- and Mission-Critical Digital Electronics,"Presented at the 2006 PMA 201 Fuze IPT System Safety Working Group, March 7-9, 2006, Oxnard, California.
- "Laser-Induced Latchup Screening and Mitigation in CMOS Devices," RADECS 2005, the 8th European Conference on Radiation and Its Effects on Components and Systems, Palais des Congrès, Cap d'Agde, France, September 19 to 23, 2005.
- "Summary of FPGA Reliability Testing," 2005 MAPLD International Conference, Washington, D.C., September 7-9, 2005.
- "This Is What We Find In This Stuff," FY2005 Software/Complex Electronic Hardware Standardization Conference, Norfolk, Virginia July 26-28, 2005
- "RTSX-S and RTSX-SU Reliability Test Vehicles," Mil/Aero Applications of Programmable Logic Devices (MAPLD) International Conference, 2004.
- "Design of Memory Systems for Spaceborne Computers," Mil/Aero Applications of Programmable Logic Devices (MAPLD) International Conference, 2004.
- "Propagation Delay Stability in Logic Devices," Mil/Aero Applications of Programmable Logic Devices (MAPLD) International Conference, 2004.
- "Total Dose and Single Event Tests and Results of a Radiation Tolerant 0.15 µm Antifuse-based FPGA," Mil/Aero Applications of Programmable Logic Devices (MAPLD) International Conference, 2004.
- Single Event Upset and Hardening in 0.15 µm Antifuse-Based Field Programmable Gate Array, 2003 IEEE Nuclear Space Radiation Effects Conference, Monterey, California, July 2003.
- The Failure of a Small Satellite and the Loss of a Space Science Mission, Keynote address at the 2002 NASA/DoD Conference on Evolvable Hardware, July 15-18, 2002, Alexandria, Virgnia.
- Single Event Effects of a FLASH-based FPGA, Thirteenth Biennial Single Effects Symposium, Manhattan Beach, CA, April 23-25, 2002
- Radiation Tolerant Antifuse FPGA, HEART/GOMAC, 2002.
- Single Event and Total Dose Effects on SEU hardened Antifuse FPGA, Mil/Aero Applications of Programmable Logic Devices (MAPLD) International Conference, 2001.
- Recent Radiation Test Results for Programmable Devices, Mil/Aero Applications of Programmable Logic Devices (MAPLD) International Conference, 2001.
- Analog and Digital Single Event Effects Experiments in Space, IEEE NSREC 2001.
- An SEU-Hard Flip-Flop for Antifuse FPGAs, IEEE NSREC 2001.
- New Instrumentation, Patterns and Their Effects on TID Testing of Antifused-Based FPGAs, IEEE NSREC 2001.
- Faster, Better, Cheaper Space Flight Electronics - An Analytical Case Study, Mil/Aero Applications of Programmable Logic Devices (MAPLD) International Conference, 2000.
- Sequential Circuit Design for Spaceborne and Critical Electronics, Mil/Aero Applications of Programmable Logic Devices (MAPLD) International Conference, 2000.
- Radiation Effects on Flash Memory-Based FPGA, Mil/Aero Applications of Programmable Logic Devices (MAPLD) International Conference, 2000.
- Radiation-Hardened/High-Reliability Programmable Logic Using Modified Commercial-off-the-Shelf Technology, Mil/Aero Applications of Programmable Logic Devices (MAPLD) International Conference, 2000.
- In Situ Parametric and Functional Testing for Total Dose Testing, Mil/Aero Applications of Programmable Logic Devices (MAPLD) International Conference, 2000.
- Analysis, Design, and Performance of Electronics In a Deep Space, High Radiation Environment, IEEE NSREC 2000.
- Recent Data on Programmable Devices and Related Technologies, IEEE NSREC 2000.
- Clock Buffer Circuit Soft Errors in Antifuse Based FPGAs, IEEE NSREC 2000/IEEE Transactions on Nuclear Science, vol. 47, no. 6, p.2675-2681, Dec. 2000
- New and Existing Microelectronics Technologies, Electronic Parts and Packaging for Space and Aeronautic Applications, Advanced Technology Workshop. May 2000.
- Single Event Latchup in 0.25µm Antifuse FPGA by 3D-Device Simulation, 12th Biannual Single Event Effects Symposium, April, 2000.
- Invited Talk, The Failure of a Small Satellite and the Loss of a Space Science Mission, Surrey Space Center Guest Lecture Series 2000, August, 2000.
- Total dose and dose-rate effects on start-up current in antifuse FPGA, RADECS ’99.
- Reconfigurable, System-on-Chip, High-Speed Data Processing and Data Handling Electronics, Mil/Aero Applications of Programmable Logic Devices International Conference, 1999.
- Logic Design Pathology and Space Flight Electronics, Mil/Aero Applications of Programmable Logic Devices International Conference, 1999. A different version of the presentation and paper were presented at ESCCON 2000, Noordwijk, The Netherlands, 2000.
- 0.25 UM Flash Memory Based FPGA for Space Applications, Mil/Aero Applications of Programmable Logic Devices International Conference, 1999.
- FPGAs in Space Environment and Design Techniques, Mil/Aero Applications of Programmable Logic Devices International Conference, 1999.
- Total dose and SEE of Metal-to-Metal Antifuse FPGA, Mil/Aero Applications of Programmable Logic Devices International Conference, 1999.
- The Impact of Software and CAE Tools on SEU in Field Programmable Gate Arrays, IEEE Transactions on Nuclear Science, 1999.
- The Effects of Architecture and Process on the Hardness of Programmable Technologies
, IEEE Transactions on Nuclear Science, 1999.- Reprogrammable FPGA for Space Applications
, IEEE Transactions on Nuclear Science, 1999. Modifications of COTS FPGA Devices for Space Applications, Mil/Aero Applications of Programmable Logic Devices International Conference, 1998.- Development of Total Dose Hardened Antifuse FPGA, Mil/Aero Applications of Programmable Logic Devices International Conference, 1998.
- Current Radiation Issues for Programmable Elements and Devices, IEEE Transactions on Nuclear Science, 1998.
- Radiation Effects on Current Field Programmable Technologies
, IEEE Transactions on Nuclear Science, 1997.- Antifuse FPGA for Space Applications
, RADECS ’97.- Programmable Logic Application Notes
, This column has appeared quarterly since 1995 in NASA EEE Links. Features the latest research, design, analysis, reliability, and radiation data on FPGAs and other programmable devices and elements for space-flight use.- Rad-Hard/Hi-Rel FPGA
, 3rd ESA Conference On Space Flight Parts, 1997.- STRV-1d SEE Flight Experiments: Digital Electronics and Optocouplers,
Single Event Effects Symposium, 1998- Sub-micron FPGA/ASIC Evaluation and SEE Issues,
Single Event Effects Symposium, 1998.- Design Techniques for Radiation-Hardened Field Programmable Gate Arrays
, Application Note, 1996.- On Data for Anti-Fuse/FPGA Reliability in the Heavy Ion Environment
, IEEE Transactions on Nuclear Science, 1995.- An Experimental Survey of Heavy Ion Induced Dielectric Rupture in Actel Field Programmable Gate Arrays
, RADECS ’95.- Total Dose Response of Actel 1020B and 1280A Field Programmable Gate Arrays
, RADECS ’95.- Diagnosis of Multiple Faults Using IDDQ Techniques
, International Test Conference IDDQ Workshop, 1995.- SEU Hardening of Field Programmable Gate Arrays (FPGAs) for Space Applications and Device Characterization
, IEEE Transactions on Nuclear Science, 1994.
The following NASA Tech Briefs:
- KPP - A VHDL Preprocessor
K-Latch: An SEU-Hard Flip-Flop Element 29KPL154 - A Small, Configurable Processor Fourth-Generation Software for SEU Testing SFI - SEU Analysis with Error Correcting Codes, K-Bus: A Low Cost, Low Power Bus for Spacecraft Instrumentation with Remote Capability Windowing System for Test and Simulation Redundancy Protects Against SEUs in Flip-Flops in FPGAs Universal FPGA Burn-In Boards GFI - Easy PC Graphics Low-Jitter Digital Rate Multiplier MIL-STD-1553B Bus Architecture for a Fault Tolerant, Loosely Coupled Multiprocessor Spacecraft Computer Fail-Safe Synchronizer Circuits for Power Supplies Selectable Telemetry Coding using a Data Synthesis Technique with Minimal Signal Distortion for Compact , Spacecraft ApplicationsCompact Implementation of a Memory Spare Row Decoder Using Standard IC’s http://www.klabs.org A www site dedicated to the research, development, and use of programmable logic and elements for space-flight applications.
HONORS AND PROFESSIONAL SOCIETIES:
- Guest Editor, Selected Papers from SPL 2008.
- Chair, Special Session "Programmable Logic in High Reliability Applications," IV Southern Conference on Programmable Logic, 2008, Bariloche, Argentina.
- 2008 Program Committee, IV Southern Conference on Programmable Logic, 2008, Bariloche, Argentina
- 2006 NASA Engineering and Safety Center (NESC) Director's Award
- 2006 Performance Award
- 2006 Special Act Award
- 2004 One NASA Award
- 2004 NASA Engineering Achievement Award
- 2003 NASA Exceptional Achievement Award
- 2003 NASA Excellence in Outreach Award
- Chairman, Military and Aerospace Applications of Programmable Logic Devices (MAPLD) International Conference. 1998 - 2006.
- Advanced Avionics Technology Working Group
- Program Committee Member, NASA Workshop on Evolvable Hardware, 1999, 2000, 2001.
- Co-Chairman, NASA/DoD Workshop on Evolvable Hardware, 2002.
- Program Committee Member, Engineering of Reconfigurable Systems and Algorithms, 2001, 2003.
- Peer Reviewer, AIAA Journal of Spacecraft and Rockets, 2001, 2003.
- Peer Reviewer, IEEE Transactions on Nuclear Science, 2000.
- Peer Reviewer, RADECS, 1999, 2001.
- Peer Reviewer, IEEE Nuclear Space Radiation Effects Conference, 1998, 1999, 2000, 2003.
- Peer Reviewer, Nuclear Instruments and Methods in Physics Research
- Numerous NASA awards for space-flight hardware delivery and performance.
- Senior Member, AIAA.
- Member, AIAA Digital Avionics Technical Committee
KEY SPACE-FLIGHT PROJECTS:
Lunar Reconnaissance Orbiter: Lunar Orbiter Laser Altimeter
Solar Dynamics Observatory (SDO), Ka-band Transmitter
NESC Independent Testing of Field Programmable Gate Arrays (FPGAs)
Industry Tiger Team, FPGA Reliability
Cockpit Avionics Upgrade Tiger Team, FPGA Applications
Small Diameter Bomb Independent Assessment Team
FPGA Reliability Independent Assessment Team (MER, MRO).
DAWN Laser Altimer: Range Measurement Unit design
Astro-E2: Independent Review and Analysis
AURA: Residual Risks Caucus
GALEX: Independent Assessment Team
HIRDLS Independent Assessment Team
GLAST Independent Assessment Team
ST-5 Independent Assessment Team
Second Generation Reusable Launch Vehicle: Independent Technology Risk Assessment Team.
GRACE: Independent Assessment Team
SORCE: Independent Assessment Team
Messenger MLA: Range Measurement Unit design
Mars Odyssey: Independent Assessment Team
HETE-2: Independent Assessment Team
WIRE: Lead investigator for failure mechanism.
Galileo: Design/test engineer for attitude control electronics.
Magellan: Design/test engineer for attitude control electronics.
Magellan: Lead engineer for synthetic aperture radar digital units.
Intelsat VII: Consultant for digital electronics.
ISTP: Instrumentation, particle detectors, facility electronics, and high-voltage power supplies for WIND and Polar instruments.
Cassini: Algorithms and circuits for several science instruments.
SMEX/FAST: Uplink, Downlink, and ACS card designs.
IR Polaris: Detector array timing & control, data acquisition, for infrared camera.
MOLA-II: Mars Global Surveyor instrument. Laser timing, clocking, and control; improved oven 100 MHz oscillator.
IRAC/SIRTF:Digital signal processor design.
XRS: S/C Communications. MIL-STD-1553B and RS-422 interface design.
EO-1: High-speed back plane chipset design. 32-bit bus and ‘standard’ functions.
Hydrostar: High-speed digital signal processor design for cross-correlators and FIR filters.
Radiation Test and analysis of advanced components: Programmables, ASICs, high-speed memories, high-speed ADC’s, high-precision DACs, programmable substrates, antifuses.
MPTB: Flight test of advanced technology FPGAs.
STRV-1d: Flight test of advanced technology programmables (memories, PAL, FPGA, programmable substrate, etc.).
DDF Director Discretionary Fund: Principal Investigator for radiation shielding, KGD, and antifuse reliability research and development projects. Recently awarded study for FPGA-based System on Chip for Space Flight Applications.
Home - NASA
Office of Logic Design
Last Revised:
November 08, 2007
Digital Engineering
Institute
Web Grunt: Richard
Katz
