OBJECTIVES

Apply my technical skills in the support of chip and system designs.

• Author of advanced and recommended VHDL books

• Real Chip Design and Verification Using Verilog and VHDL, 2002, ISBN 0-9705394-2-8
• Component Design by Example, ... a Step-by-Step Process Using VHDL with UART as Vehicle,  2001
• VHDL Coding Styles and Methodologies, 1^st & 2nd Edition, 1995 & 1999
• VHDL Answers to Frequently Asked Questions, 1^st & 2nd Edition

• Supported design organizations in:

• Applications of VHDL
• Synthesis methodologies
• Verification Methodologies
• Process design flows
• RTL designs/synthesis
• Testbench designs
• EDA Tool evaluations

• Pilot Team member for development of 1076.6 Standard for VHDL Register Transfer Level Synthesis Level 1 (completed) and Level II (in progress).
• Trained over 500 students in the application of VHDL for synthesis and testbench designs.
• Instructor of several courses on application of microprocessors (USC), microprogramming, and Pascal.
• Experienced is several modeling languages: C, Pascal, Ada, CACI Simscript, ECSS, CACI Network II.5, SES Workbench, Foresight.
• Experienced in Synopsys Design Compiler and Experienced in Synplicity's Synplify.
• Experienced in ModelSim and Leapfrog simulators.
• Evaluated and used Novas Debussy's debugging tools.
• Performed several hardware designs from proposals through production.

WORK HISTORY

Hughes Aircraft / Raytheon from 1967 through April 2000.

EDUCATION

MSEE, 1972, University of Southern California.
Communications Theory.