NASA Office of Logic Design

A scientific study of the problems of digital engineering for space flight systems,
with a view to their practical solution.

LVDS DS90C031 Heavy Ion SEL Test

Brookhaven National Labs

September, 1999

Test Results Summary

Heavy ion tests were run on the National Semiconductor DS90C031 LVDS driver.  These devices were modified to eliminate the latchup sensitivity they have shown in previous versions and heavy ion tests.  The DUTs for this test were in flat packs and mounted on a controlled impedance (100 ohm) printed circuit board.  Previous tests used SOIC and LCC packages.  The die are identified as DS90C031D by optical examination using a microscope.

No latchups were observed during these test runs.  Three units were tested and all runs were at maximum voltage (5.5VDC), worst-case for the single event latchup (SEL) test.  Both data patterns (zeros and ones) were used.  High fluences were used, typically 4 x 10⁷ ions/cm² per run, to ensure a thorough test of this modified device.  Details are in the data table below.  No functional failures or damage was detected.

Some Single Event Transient (SET) data was obtained and the data is located in the table below.  A graph of SET Cross-section vs. LET was not made since the parts were not tested at either nominal or low voltage.  Hence, the data is supplied only for reference.  The circuit configuration may also underestimate the SET rate; the four driver receiver pairs per device are wired in series.  The output of the last receiver (DS90C032) is monitored in two ways.  The first simply goes to a relatively slow RS-422 driver, a DS26C31, which sends the signal down a long cable (50 to 100 feet twisted pair), into a DS26C32 RS-422 receiver, then into a counter implemented in an Altera 5192.  The final contents of this counter are listed in "Upsets Slow."  We expected, and observed, that the slow interface would act as a filter.  The clock input of a 74AC109 was used as a fast transient pulse detector.   This data is shown in the column labelled "Upsets All" and is a better indicator of the SET rate.  It will underestimate a bit as the 4 series connected driver-receiver pairs may act as a filter.  Beam time limitations during this trip prevented a full SET characterization as well as testing at lower LETs to find the SET threshold - the primary objective of this test was to verify the SEL design fix.  Our next test date in December, 1999, will perform an SET characterization.   Additionally, transient waveforms will be captured to determine pulse amplitudes and widths.

The chart below is not perfectly formatted - unfortunately I do not have time to make it pretty as I am fighting the <insert your favorite s/w manufacturer's name here> software and their products are not mutually compatible.  The last few weeks have been quite busy.  If you have any difficulty reading the table (it appears OK using Netscape on my terminal) please e-mail me and I'll either fix it or send out the data in .xls format.

Test Results Data

Run Name:    BNL0999

Part #:          DS90C031, Revision D

Package:       Flatpack

Test Facility: BNL

Home - NASA Office of Logic Design
Last Revised: April 10, 2004
Digital Engineering Institute
Web Grunt: Richard Katz