NASA Office of Logic Design

A scientific study of the problems of digital engineering for space flight systems,
with a view to their practical solution.

2002 Non-volatile Memory Technology Symposium Proceedings

November 4-6, 2002

The Missions of the Jet Propulsion Laboratory David Crisp, Jet Propulsion Laboratory Presentation: 01_crisp.pdf
The Future of NonVolatile Memories T. Mikolajick, Infineon Abstract: 02_mikolajic_a.pdf Presentation: 02_mikolajic_s.pdf Paper: 02_mikolajic_p.pdf	Abstract –– In this paper the ongoing research and development activities on future nonvolatile memory technologies are described. After reviewing the mainstream nonvolatile memories on the market today, memory concepts based on switching effects in inorganic and organic materials as well as in single molecules are summarized. Finally the pros and cons are compared and conclusions for the near, mid and long-term perspectives are drawn. today. Moreover, much higher data densities than the present ones will be required for storing multi media data like videos. This calls for a memory with an extremely small bit cell size. To achieve these goals, novel materials showing new switching mechanisms have to be introduced into the CMOS process flow. Fig. 1 shows the hierarchy of possible CMOS memory material extensions used as a basis for the following discussion
System and Economic Requirements for Advanced Non-Volatile Memories R. Andrei, Web-Feet Research Abstract: 03_andrei_a.pdf Presentation: 03_andrei_s.pdf Paper: 03_andrei_p.pdf	Abstract Modern computing system architectures are inhibited by memory limitations: volatility, low density compared with system needs, low speed compared with CPU speed and high cost compared with the cost of mechanical storage. The lack of memory technologies that satisfy even a subset of the system requirements has forced designers to work around these limitations by creating complex multi-layered memory systems at the expense of system performance and cost.
Embedded Memory Technologies - the First Step Towards SoC R. Andrei, Web-Feet Research Abstract: 04_andrei_a.pdf Presentation: 04_andrei_s.pdf Paper: 04_andrei_p.pdf	Abstract Over the last four decades, the semiconductor industry has created four basic types of product classes which are identified also as sub-systems: MPU (which is representative for logic), ASIC/FPGA (for field programmability), DRAM (for memories) and AMS (for analog/mixed signal). The need to continuously improve these product classes has lead to optimized sub-system performance and cost to the detriment of system performance and cost.
Rugged & Reliable Data Storage: Choosing the Right Media for Rugged COTS Mass Data Storage O. Tzur, M-Systems Abstract: 05_yzur_a.pdf Presentation: 05_dan_s.pdf Paper: 05_yzur_p.pdf	Abstract The cost and time of customizing data storage for military and space systems, on the one hand, and of assessing the potential risks of using COTS to achieve required ruggedization and reliability levels, on the other hand, continues to be a central issue for designers of mission-critical applications. Although it is clear that hard disks are inappropriate for military systems due to their inherent reliability problems under harsh environment conditions (rotating mechanical heads), other COTS data storage products are available that meet mission-critical requirements. This article discusses the pros and cons of COTS solutions for mass storage, including ruggedized mechanical hard disks and solid-state flash disks. Aspects such as environmental specifications, endurance, data reliability, data security as well as costs of each alternative are also discussed.
High Speed, Radiation Hard MRAM Buffer R. Sinclair, NVE Corp. Abstract: 06_sinclair_a.pdf Presentation: 06_sinclair_s.pdf Paper: 06_sinclair_p.pdf	Abstract AbstractŒŒRadiation hardened nonvolatile memory has many applications in DoD military, space systems, MILSATCOM, and commercial space systems. However, most nonvolatile memory components that exist today do not fully meet the requirements of these applications. A novel, low power, Magnetoresistive Random Access Memory (MRAM), that uses a Sandwich-Spin Dependent Tunneling (SSDT) memory bit and that meets all of the application requirements, is described. The SSDT bit combines a sandwich storage structure with tunneling magnetoresistance readout. A single, bi-polar write current is used to write the bit. A write select transistor, in the memory cell, selects a single bit for writing - thereby eliminating half-select conditions. Antiferromagnetic coupling in the sandwich film minimizes the required switching field, leading to low write currents - as low as 4 mA seen in 2 µm devices and 0.8 mA predicted for an 0.6 µm device. A two bit, differential cell, is being used to design a 1k buffer memory, memory, that will use SDT memory elements that have been radiation tested to over 1 Mrad.
Invited Talk:  Remembering the Past from the Depths of Space K. Clark, Jet Propulsion Laboratory Presentation: 07_clark_s.pdf
Compact Holographic Memory Using E-O Beam Steering Technology T-H Chao, Jet Propulsion Laboratory Abstract: 08_chao_a.pdf Presentation: 08_chao_s.pdf Paper: 08_chao_p.pdf	Abstract An innovative holographic memory system has been developed at JPL for high-density and high-speed data storage in a space environment. This system utilizes a newly developed electro-optic (E-O) beam steering technology for beam steering to enable high-speed random access memory read/write without moving parts. A compact CD-sized holographic memory breadboard was built and demonstrated for holographic data storage and retrieval. Details regarding technical progress is presented in this paper.
High Performance Organic Non-Volatile Memory Device ----a Direct Challenge to the Si Technology Y. Yang, University of California at Los Angeles Abstract: 09_ma_a.pdf Presentation: 09_ma_s.pdf Paper: 09_ma_p.pdf	Introduction Electrical bistability is a phenomenon in which a device exhibits two states of different conductivities at the same applied voltage, which is promising for switch and memory devices application. We demonstrate a high performance organic electrical bistable device (OBD) with the structure of organic/metal/organic multi-layers interposed between two electrodes [1,2].
The Transpinnor®: An Active Spin-Based Device E. Torok, Integrated Magnetoelectronics Abstract: 10_spitzer_a.pdf Presentation: 10_spitzer_s.pdf Paper: 10_spitzer_p.pdf	Abstract - We report the operation at room temperature of an all-metal, active device based on electron spin, which we call the transpinnor 1,2 . A transpinnor is a bridge of four electrically connected GMR (giant magnetoresistive) films whose resistance is controlled by the magnetic field from the current in one or more input striplines electrically isolated from the GMR films. The GMR elements are also connected to power terminals. When the transpinnor is resistively balanced its output remains zero even with power applied to it. A current in an input stripline unbalances the bridge and produces an output that depends on the power current. Transpinnors can be used as selection-matrix elements for magnetic memories, for logic elements of all kinds (e.g., AND, OR, XOR, NAND, NOT), for amplifiers, differential amplifiers, and magnetometers. Experimental results on integrated transpinnors will be presented, demonstrating its utility for logic, analog circuits, and amplification. We have also simulated the function and performance of various small-scale-integration (SSI) logic elements, based on measured GMR film properties. The aim was to verify functionality for a representative set of the SSI elements and to characterize all properties needed to design systems. Simulation results established that transpinnor logic gates are suitable as building blocks in large systems. The all-metal aspect of the transpinnor is unique. Unlike the mixed-technology systems that implement spin-based logic using both semiconductors and ferromagnets, transpinnor-based circuits are fabricated using only metal depositions on a monolithic chip; mixed technology requires fabricating semiconductor and magnetic elements on the same chip. All-metal devices have significant cost, design, manufacturing, and performance advantages over mixed ferromagnetic/semiconductor systems: higher performance, lower power, low costs, inherent radiation hardness; the number of masking steps in all-metal magnetic-RAM processing is about one-third that in its mixed-technology counterpart. Transpinnors have been used to design a number of different all-metal logic gates and circuits, as well as amplifiers and selection circuitry for a 1 Mbit all-metal (support circuitry as well as memory array) magnetic RAM presently being fabricated.
Static FRAM: A Novel Ferroelectric Memory Approach J. Evans, Radiant Technology Abstract: 11_bell_a.pdf Presentation: 11_bell_s.pdf Paper: 11_bell_p.pdf	Abstract Nonvolatile memory based on thin ferroelectric film capacitors has become available commercially in increasing density now reaching 256Kb. Reseachers have begun to examine new memory elements consisting of transistors fabricated with the ferroelectric material in the gate to control current flow in the transistor channel. While most published research has concentrated on building ferroelectric gates on CMOS transistors, Radiant has explored thin ferroelectric film transistors similar to those used in TFT-LCDs. The devices are fabricated as a ferroelectric capacitor with an oxide semiconductor, not silicon, as one of the electrodes. If the semiconducting electrode is thin enough, the ferroelectric polarization will modulate its conductivity. While it is not possible to use these devices as logic gates, they can produce ON/OFF ratios up to 100 in conductivity while being read with voltages as low as 10mV. Write times less than 100ns in cell areas rivaling SRAM are possible. An attractive application for the SFRAM transistor is in ultra-low power non-volatile memories.
Enabling MLC NAND Flash for Cost-Effective, High Capacity Data Storage R. Dan, M-Systems Abstract: 12_dan_a.pdf Presentation: 12_dan_s.pdf Paper: 12_dan_p.pdf	Abstract The more functionality that OEMs offer users to support applications such as moving maps, tactical computers and airborne systems, the more memory capacity that is required to store additional applications and user data -reliably, cost-effectively, and space-effectively. To meet these demands, OEMs are encouraging flash memory manufacturers to implement advanced technologies that can provide the performance and reliability of a big system in a low-cost, small-as-possible package. Among the technologies that flash memory manufacturers are investigating is Multi-Level Cell (MLC) technology. MLC technology offers double the bit storage capacity per cell, reducing the total die size. This has a major impact on the silicon cost. On the surface, MLC looks like the perfect solution. But without highly reliable and efficient algorithms to guarantee data reliability and some mechanism to boost MLC performance, much lower than standard NAND-based performance, MLC technology can meet neither reliability nor performance requirements. Working closely with Toshiba, M-Systems developed and patented x2 technology to enable MLC as a local memory storage solution, without compromising reliability and achieving performance rates that rival and even exceed standard NAND-based flash technology rates. This paper explains how M-Systems’ x2 technology achieves this.
Invited Talk: Inadvertently Programmed Bits in Samsung 128 Mbit Flash Devices - A Flaky Investigation G. Swift, JPL Presentation: 13_swift_s.pdf Paper: 13_swift_p.pdf	Abstract JPL ’s X2000 avionics design pioneers new territory by specifying a non-volatile memory (NVM)board based on flash memories. The Samsung 128-Mb device chosen was found to demonstrate bit errors (mostly program disturbs)and block-erase failures that increase with cycling.Low temperature,certain pseudo- random patterns,and,probably,higher bias increase the observable bit errors.An experiment was conducted to determine the wearout dependence of the bit errors to 100 k cycles at cold temperature using flight-lot devices (some pre-irradiated).The results show an exponential growth rate,a wide part-to-part variation,and some annealing behavior.
Invited Talk: Description and Reliability of a Robust 0.18 micron Low Voltage and Low Power Embedded Flash Technology A. Khan, Philips Semiconductor Presentation: 14_kahn_s.pdf Paper: 14_kahn_p.pdf	Abstract Philips Semiconductors has developed a 0.18u, triple-well, embedded Flash technology. The basic technology uses a 2T cell, FN-FN program/erase, on-chip charge pumps for Program/erase voltage generation and operates over a 1.2 to 2V range (read). Design techniques, the flash cell and the process are optimized to produce a robust product with high endurance over a wide range of operating conditions. Program/Erase voltage condition of selected and un-selected cells are optimized for robustness. Extensive reliability studies have been performed and data will be presented to show performance meets expectations in such critical areas as Bit Disturb characteristics, Endurance, and Data retention. The system advantages of this approach, applications and future technology paths are briefly described.
Invited Talk:  Utilization of Advanced Microelectronics in Space Applications S. Kayali, Jet Propulsion Laboratory Presentation: 15_kayali_s.pdf	Outline About JPL Industry Trends & Challenges Environments and Reliability Trends at JPL Parts Evaluation Practices at JPL Considerations for Radiation Effects Conclusions
Reliability and Endurance of FRAM: A case study J. Namkung, JPL Presentation: 16_namkung_s.pdf Paper: 16_namkung_p.pdf	Abstract This paper describes a case study quantifying reliability and endurance results of two FRAM nonvolatile memories. The need for reliability and endurance testing is vital to space applications where single event upsets (SEUs) can occur in memory and disrupt or disable a flight system. The method used to test the ferroelectric nonvolatile memory FRAM chips incorporates a XILINX XC4010E FPGA performing reads/writes to the memory chips and a PC in tandem to record errors. This method is extremely low cost and comparable in test times to commercially available memory testers with high hourly rates.
Evaluation of Data Retention and Imprint Characteristics of FRAMs Under Environmental Stresses for NASA Applications A. Sharma, Goddard Space Flight Center Abstract: 17_sharma_a.pdf Presentation: 17_sharma_s.pdf Paper: 17_sharma_p.pdf	Abstract A major reliability issue for all advanced nonvolatile memory (NVM) technology devices including FRAMs is the data retention characteristics over extended period of time, under environmental stresses and exposure to total ionizing dose (TID) radiation effects. For this testing, 256 Kb FRAMs in 28-pin plastic DIPs, rated for industrial grade temperature range of -40 °C to +85 °C, were procured. These are two-transistor, two-capacitor (2T-2C) design FRAMs. In addition to data retention characteristics, the parts were also evaluated for imprint failures, which are defined as the failure of cells to change from a "preferred" state, where it has been for a significant period of time to an opposite state (e.g., from 1 to 0, or 0 to 1). These 256 K FRAMs were subjected to scanning acoustic microscopy (C-SAM); 1,000 temperature cycles from -65 °C to +150 °C; high temperature aging at 150 °C, 175 °C, and 200 °C for 1,000 hours; highly accelerated stress test (HAST) for 500 hours; 1,000 hours of operational life test at 125 °C; and total ionizing dose radiation testing. As a preconditioning, 10 K read/write cycles were performed on all devices. Interim electrical measurements were performed throughout this characterization, including special imprint testing and final electrical testing. Some failures were observed during high temperature aging test at 200 °C, during HAST testing, and during 1,000 hours of operational life at 125 °C. The parts passed 10 Krad exposure, but began showing power supply current increases during the dose increment from 10 Krad to 30 Krad, and at 40 Krad severe data retention and parametric failures were observed. Failures from various environmental group testing are currently being analyzed.
Tunneling Phenomenon in SuperFlash® Cell A. Kotov, Silicon Storage Technology Abstract: 18_kotov_a.pdf Presentation: 18_kotov_s.pdf Paper: 18_kotov_p.pdf	Abstract An extensive investigation of interpoly oxide conduction (erase) mechanism for SuperFlash cell is presented. Single electron tunneling events have been detected, using regular flash memory cell. A physical model based on cylindrical approximation for the Fowler-Nordheim equation has been developed which shows good agreement with experimental data. The model includes two fitting parameters: SiO2/poly-Si barrier height and average radius of curvature of the FG (Floating Gate) tunnel injector edge. Erase voltage distribution appears to be better described by modification of the SiO2/poly-Si barrier rather than by process-related variations of the FG injector radius. In this paper the authors also present an accurate single cell technique for measuring coupling ratio (CR) concurrently with forward and reverse tunneling voltages between control and floating gates of the SuperFlash cell. As opposed to conventional techniques for the CR characterization, a new technique does not require a reference cell with contacted floating gate for CR measurement
Radiation Testing of EEPROM Embedded in a 3 GHz Phase Locked Loop M. Burgener, Peregrine Semiconductor Abstract: 19_burgener_a.pdf Presentation: 19_burgener_s.pdf Paper: 19_burgener_p.pdf	Abstract EEPROM is widely used in wireless systems for customization of IC functions and storage of system specific data. In this paper we report, for the first time, EEPROM capability embedded in a high performance RF product, including initial radiation testing of the EEPROM cells. The programmable PLL operates to 3 GHz, which requires a high performance RFIC technology. This is the first time EEPROM and its programming circuitry has been integrated into multi- GHz RFIC products. We report the radiation performance of the embedded EEPROM cell, including programming reliability up to 100 krad. We present the basic cell read and write mechanism, basic storage architecture, write and erase conditions, and methods of dealing with ESD when both low and high voltage pulses are required to program the device. Pre- and post-irradiation parameters are presented.
Single Event Effect and Total Ionizing Dose Response of Emerging Non-Volatile Memories D. Nguyen, Jet Propulsion Laboratory PRESENTER: LEIF SCHEICK Abstract: 20_nguyen_a.pdf Presentation: 20_nguyen_s.pdf Paper: 20_nguyen_p.pdf	Abstract We report on the Single Event Effect (SEE) and Total Ionizing Dose (TID) tests of higher density flash memories. Stand-by currents and functionality tests were used to characterize the response of radiation effects. Single Event Functional Interrupt (SEFI) errors were observed, indicating upsets from complex control circuitry.
Single Event Effect Evaluation of FeRAM Memories for Space Applications L. Scheick, Jet Propulsion Laboratory Abstract: 21_scheick_a.pdf Presentation: 21_scheick_s.pdf Paper: 21_scheick_p.pdf	Abstract Single Event Upset (SEU) and Single Event Latch-up (SEL)cross-sections were obtained for two different Ferroelectric Random Access Memories (FeRAM) memories: The 64-kbit and 256-kbit Ramtron FeRAM and the Hynix 64-kbit device.  The devices were seen to have latch-up characteristics typical of commercial Complimentary Metal Oxide Silicon (CMOS) devices. Also, errors in the memory were also seen from heavy ion irradiation.
Invited Talk: Non-Volatile Parameters - The Good, The Bad, The Ugly K. Hunt, AFRL Presentation: 22_hunt_s.pdf
Integration and Circuit Demonstration of Chalcogenide Memory Elements with a Radiation Hardened CMOS Technology J. Rodgers, BAE Systems Abstract: 23_rodgers_a.pdf Presentation: 23_rodgers_s.pdf Paper: 23_rodgers_p.pdf	Abstract BAE SYSTEMS in Manassas, Virginia, and Ovonyx, Inc., have previously reported electrical test results from stand-alone single-bit chalcogenide memories. In this paper we present a description of two test chips, one that has been used to integrate the chalcogenide memory element with BAE SYSTEMS’ radiation hardened 0.5 µm CMOS technology, and another to develop 64 kbit arrays with full write-read circuitry suitable for environmental and radiation testing. Electrical test results from these test chips will be presented showing full functionality.
Low Power 256K MRAM Design R. Beech, NVE Corp. Abstract: 24_beech_a.pdf Presentation: 24_beech_s.pdf Paper: 24_beech_p.pdf	Abstract A low power Magnetoresistive Random Ac- cess Memory (MRAM), that uses a novel Sandwich-Spin Dependent Tunneling (SSDT) memory bit is described. The SSDT bit combines a sandwich storage structure with tunneling magnetoresistance readout. A single, bi-polar write current is used to write the bit. A write select tran- sistor, in the memory cell, selects a single bit for writing - thereby eliminating half-select conditions. Antiferromag- netic coupling in the sandwich film minimizes the re- quired switching field, leading to low write currents - as low as 4 mA seen in 2 µm devices and 0.8 mA predicted for an 0.6 µm device. A two bit, differential cell, has been used to design a 256k memory.
MRAM Design Limitations Dictated by Thermally Activiated Reversal J. Zhu, Carnegie Mellon University Abstract: 25_zhu_a.pdf Presentation: 25_zhu_s.pdf mp1.mpeg mp2.mpeg	Outline Introduction Modeling of Thermal Excitation in MTJ Memory Elements Thermally Excited Ferromagnetic Resonance Switching Probability for Half-Select Elements Storage Layer Thickness and Area Storage Density Analysis on VMRAM Designs Conclusions
Reproducible Electric-Pulse Induced Resistive (EPIR) Switch Effect of Manganite Films for Non-Volaitle Memory Applications A. Ignatiev, University of Houston Abstract: 26_ignatiev_a.pdf Presentation: 26_ignatiev_s.pdf Paper: 26_ignatiev_p.pdf	Abstract The manganite perovskite, Pr1-xCaxMnO3 (PCMO), exhibits large reproducible nonvolatile resistance changes at room temperature and without applied magnetic field when exposed to pulsed applied electric fields of varying polarity. Positive or negative voltage pulses can switch the resistance of thin films of the oxide between a low- (Rmin) and a high-impedance (Rmax) state in times shorter than 9ns. A resistance ratio P=(Rmax-Rmin)/Rmin of more than two orders of magnitude has been obtained for samples with an operating temperature range of 23 °C to 200 °C. The resistance change ratio P remains constant in the temperature range of 23 °C to 100 °C, but shows a decrease above 120 °C with major changes in P above 200 °C. An activation energy of ~110 MeV has been extracted from the Arrhenius plots for both the low and high resistance states of the material. The PCMO thin film samples were grown both by RF sputtering and by pulsed laser deposition on Pt/crystalline oxide substrates and on Pt/silicon substrates. X-ray diffraction analyses indicated that epitaxial PCMO thin films were grown on YBCO/LaAlO3(001) crystal substrates, and PCMO polycrystalline films were deposited on Pt/LaAlO3(001) and Pt/TiN/SiO2/Si substrates.  PCMO thin films on all substrates were observed to switch although the epitaxial films showed better performance in terms of both magnitude of P and voltage applied to switch. The principles underlying the electric pulse induced resistive switch effect have been analyzed, and will be discussed.
High Density NDRO Ferroelectric Memory D. Kamp, Celis Semiconductor Abstract: 27_kamp_a.pdf Presentation: 27_derbenwick_s.pdf Paper: 27_kamp_p.pdf	Abstract Very high density ferroelectric memories using ferroelectric transistors for the memory storage devices are being developed. Memory cell sizes as small as 4 F 2 to 10 F2 , where F is the minimum design rule feature size, are possible with this new technology. A ferroelectric material with a low dielectric permittivity allows appro-priate programming voltages to be applied to the non-volatile ferroelectric transistor and provides for longer retention. A simple process flow using a fully encapsu-lated ferroelectric layer enables the memories to be manu-factured on a CMOS process with aggressive design rules. By leap-frogging technology generations, FeRAMs of 128-Mbit and 256-Mbit densities may be possible within the next few years. By using a transistor for the memory storage device, non-destructive read-out (NDRO) is achieved. By combining the dense ferroelectric tech-nology with hardened-by-design CMOS peripheral cir-cuitry, very dense radiation hardened FeRAMs for space applications can become a reality.
Nonvolatile and SDRAM Ferroelectric Memories for Space Applications D. Kamp, Celis Semiconductor Abstract: 28_kamp_a.pdf Presentation: 28_derbenwick_s.pdf Paper: 28_kamp_p.pdf	Abstract A shunted ferroelectric memory cell has been designed for use in memories that are hardened to total ionizing dose and single event upset using hardened-by-design techniques. This approach eliminates the need for a radiation hardened CMOS process and allows for fabri-cation of the memories at a commercial ferroelectric semiconductor vendor. The memory cell is being used in two prototype designs, a 1-kbit nonvolatile ferroelectric memory prototype and a 4-Mbit synchronous DRAM prototype. Nonvolatile and DRAM behavior of the mem-ory cell are controlled by using different internal pro-gramming voltages. Lower programming voltages allow the SDRAM to have higher endurance levels in trade for shorter retention times as compared to the nonvolatile ferroelectric memory. The ferroelectric memory capa-citor in each memory cell is intrinsically resistant to ra-diation exposure. The success of hardening the CMOS circuitry by design techniques will be evaluated by in-vestigating both memory types for performance and radiation hardness.
FRAM: Advanced Feature Set Pulls the Technology into the High Density Domain T. Davenport, Ramtron Abstract: 29_davenport_a.pdf Presentation: 29_davenport_s.pdf Paper: 29_davenport_p.pdf	Abstract Ferroelectric integrated circuit memory, FRAM, has been in production for ten years, advancing up the VLSI density path towards ULSI. Areas in the technology’s development that have been critical in the past and will be critical in the future are discussed in this paper. These are, in the order in which they have been solved: design techniques; materials of construction; tools for fabrication; standard CMOS process compatibility, feature set definition; reliability; industry acceptance and standardization; and finally, FRAM competitiveness in the market place. Designs have advanced from early 6T2C cells to 1T1C commercial offerings at present. The path to high purity and high performance ferroelectric materials is established. Industry standard tool sets are available and can be understood in standard semiconductor terms such as cost of ownership and vendor support. Ease of integration into a conventional CMOS flow is outlined. The feature set initially focused on NVM retention attributes, but now includes other high-performance NVM qualities such as fast write, high endurance, low power, ease of integration, and perhaps most importantly in comparison to other competing technologies, high reliability. Acceptance and standardization as cast in the ITRS is critiqued. Finally the economic marketplace for FRAM is examined and a forecast made for key market drivers to understand how large the economic impact will be this decade.

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