| Title, Authors, Reference, Link | Abstract, Summary, Conclusions |
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Advances in FeRAM Technologies Gary F. Derbenwick, David A. Kamp, Stephen C. Philpy and Alan F. Isaacson Celis Semiconductor Corporation celis@celis-semi.com Presentation:
derbenwick_adv_feram_celis.pdf |
Abstract Commercial ferroelectric random access memories (FeRAMs) are emerging into the marketplace. Reliability levels have been measured to be comparable to or better than those of other reprogrammable nonvolatile semiconductor technologies. Both SBT and PZT ferroelectric materials have been used in these memories for the memory storage elements. By combining ferroelectric memory technology with radiation hardened CMOS technology, nonvolatile semiconductor memories for space applications can be attained. These memories have high endurance, fast write times and low power performance. While significant efforts are underway at major semiconductor manufacturers worldwide to develop ferroelectric memory businesses, funding limitations must be overcome to allow the development of radiation hardened ferroelectric memories for space applications. |
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SONOS Nonvolatile Shadow RAMs for Space
Applications Gary F. Derbenwick*, David A. Kamp*, Alan F. Isaacson*, J. Roger Gill** and Stephen Linn** Celis Semiconductor Corporation celis@celis-semi.com **Simtek Corporation gill@simtek.com
Presentation:
derbenwick_radhardnvsram_celis.pdf |
Abstract Several versions of shadow random access memories have been commercialized. These memories consist of an SRAM shadowed by a nonvolatile memory on a single chip of silicon. Both floating gate and silicon nitride devices have been used for the nonvolatile shadow memory storage elements. Because radiation hardened SRAMs have been proven for space applications and silicon nitride devices have a high tolerance to radiation exposure, shadow RAMs based on the silicon nitride technology can be combined with radiation hardened CMOS to provide rugged nonvolatile semiconductor memories for space applications. These memories have high endurance, fast write times and low power performance because these parameters are determined by the SRAM portion of the memory. The nonvolatile shadow memory is automatically written only on power down. Therefore the endurance limitation of silicon nitride to approximately 106 cycles applies only to the number of power down cycles. Nonvolatile retention times of greater than ten years can be obtained at 140°C. |
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SONOS Nonvolatile Semiconductor Memories for
Space and Military Applications Dennis A. Adams1, David Mavis2, James R. Murray3, and Marvin H. White4 1 Northrop Grumman Corporation 2 Mission Research Corporation 3 Sandia National Laboratories jrmurra@sandia.gov mhw0@lehigh.edu dennis_a_adams@md.northgrum.com
Presentation:
d_adams_sonos_northrop.pdf |
Abstract Silicon-Oxide-Nitride-Oxide-Silicon (SONOS) based nonvolatile memory has emerged as the most mature nonvolatile semiconductor memory (NVSM) currently in use for space applications. SONOS 64k EEPROMs have been flying in numerous satellite applications since 1992 with a 256k EEPROM version of this part qualified for space applications in 2000. This paper will summarize the production and development status of a family of SONOS-based devices (EEPROMs, FPGAs, Controller ASICs) currently being manufactured at the Northrop Grumman Corporation (NGC) Advanced Technology Laboratories in Baltimore, Maryland. |
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Challenges in Implementing Commercial Non-Volatile Memory in Spacecraft Solid State
Recorders Lynn Adams (ladams@seakr.com) Kedong Chao (kedong@seakr.com) Matt Fehringer (matt@seakr.com) Chris Miller (chrism@seakr.com) Paul Murray (paul@seakr.com) SEAKR Engineering, Inc. Presentation:
l_adams_seaker.pdf |
Abstract SEAKR Engineering produces a variety of Solid State Data Storage and Processing Systems for use in applications from avionics to deep space. Power requirements for deep space missions require the use of non-volatile storage system. For the JPL X2000 program, SEAKR selected FLASH memory for use in the PCI Non- Volatile Memory Slice (NVMS). While FLASH Memory offers a significant power advantage for interplanetary missions, there are several constraints intrinsic to FLASH memory devices that must be resolved by the system design. These features include; radiation sensitivity, slow read/write speed, bad memory blocks, limited write cycles, and electro-magnetic noise. This paper describes how these features were resolved and the tradeoffs that were made to accommodate the use of FLASH memory in an interplanetary environment. |
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Functional Nanostructured Particle Arrays for
Nanocrystal Nonvolatile Memories Harry Atwater Thomas J. Watson Laboratory of Applied Physics Presentation: presentation?????? |
Abstract See Presentation |
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Quantitative Analysis of Charge Injection and
Discharging of Si Nanocrystals and Arrays by
Electrostatic Force Microscopy L.D. Bell Jet Propulsion Laboratory, Caltech E. Boer, M. Ostraat, M.L. Brongersma, R.C. Flagan, H.A. Atwater Caltech Presentation: presentation?????? |
Abstract See Presentation |
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Total Dose Radiation Response and
High Temperature Imprint Characteristics
of Chalcogenide Memory Elements Steve Bernacki Raytheon Sudbury MA Ken Hunt, Scott Tyson AFRL Albuquerque NM Steve Hudgens, Boil Pashmakov, Wally Czubatyj Ovonyx Troy MI Presentation:
bernacki_raytheon_afrl_ovonyx.pdf |
Abstract See Presentation |
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Design Considerations in Scaled SONOS
Nonvolatile Memory Devices Jiankang Bu and Marvin H. White Sherman Fairchild Laboratory jib2@lehigh.edu mhw0@lehigh.edu Presentation:
bu_white_sonos_lehigh_univ.pdf |
Abstract Scaling the programming voltage, while still maintaining 10-year data retention time, has been always a big challenge for Poly- Oxide-Nitride-Oxide-Silicon (SONOS) researchers. We describe our progress in the design and scaling of SONOS nonvolatile memory devices. –9V +10V (1ms) programmable SONOS devices ensuring 10 years retention time after 107 Erase/Write cycles at 85°C have been developed successfully. Deuterium anneal, applied in SONOS device fabrication for the first time, improves the endurance characteristics better than traditional hydrogen or forming gas anneal. In this paper, we describe scaling considerations and process optimization along with experiments and characterization results. |
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High Density Packaging of Non-Volatile Memory John C. Carson & Keith D. Gann IRVINE SENSORS CORPORATION jcarson@irvine-sensors.com kgann@irvine-sensors.com Presentation:
carson_irvine.pdf |
Abstract We describe an innovation in three-dimensional (3D) packaging is heterogeneous stacks containing all of the components for a complete system or subsystem. The stack is constructed using known good die (KGD), and provides a high level of integration and interconnectivity. This packaging technology lends itself to mass storage, as well as complete computers and other complex systems. For non-volatile memory, very high densities can be achieved even through the individual chips themselves are relatively low capacity. |
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Advanced Compact Holographic
Data Storage System Tien-Hsin Chao, Tien-Hsin.Chao@jpl.nasa.gov Hanying Zhou, Hanying.Zhou@jpl.nasa.gov George Reyes, George.F.Reyes@jpl.nasa.gov Jet Propulsion Laboratory Presentation: Presentation??? |
Abstract JPL, under current sponsorships from NASA Space Science and Earth Science Programs, is developing a high-density, nonvolatile and rad-hard Advanced Holographic Memory (AHM) system to enable largecapacity, high-speed, low power consumption, and read/write of data in a space environment. The entire read/write operation will be controlled with electro-optic mechanism without any moving parts. This CHDS will consist of laser diodes, photorefractive crystal, spatial light modulator, photodetector array, and I/O electronic interface. In operation, pages of information would be recorded and retrieved with random access and highspeed. The nonvolatile, rad-hard characteristics of the holographic memory will provide a revolutionary memory technology to enhance mission capabilities for all NASA’s Earth Science Mission. In this paper, recent technology progress in developing this CHDS at JPL will be presented. The recent applications of the CHDS to optical pattern recognition systems as a high density, high transfer rate memory bank will also be discussed. |
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Advanced MRAM Concepts James M. Daughton Nonvolatile Electronics, Inc. daughton@nve.com
Presentation:
daughton_nve.pdf |
Abstract Two important goals of Magnetoresistive Random Access Memory (MRAM) development are to improve MRAM manufacturability and to extend MRAM density to 100 nm dimensions. One potential barrier to MRAM manufacturability is associated with the method of write selection in which two orthogonal currents in coincidence must write data, whereas each of the orthogonal currents alone cannot disturb the data. This "2D" selection method places constraints on uniformity of MRAM memory cells. Using a transistor per cell for write select greatly improves operating margins and lowers write currents. Attaining reasonable memory densities for this scheme depends on limiting the required write current in order to minimize the area of the select transistor. A second goal is to extend MRAM density to 100 nm dimensions. Use of a vertical GMR multilayer ring structure, where the data is stored in circumferencially oriented magnetizations, can extend the density of MRAM [Zhu and Prinz, Paper GB-02, 1999 Intermag]. Stability is projected for cells with inside diameters of less than 50nm. A second approach is to use Joule heating, in combination with magnetic field from a current, to write by exceeding the Neel point of an antiferromagnetic pinning layer in a pseudo-spin valve cell. Feature sizes smaller than 100 nm are projected along with decreases in required switching currents. |
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A 0.25µm Embedded Flash Technology with Shallow Trench Isolation
Using Channel FN Operation C.J. Huang, Y.C. Liu, P.C. Lin, A Wu, H.H. Chen, W.C. Ting and Gray Hong Specialty Technology Division United Microelectronics Corporation No. 3, Li-Hsin Rd. 2 Science-Based Industrial Park Hsin Chu, Taiwan, R.O.C. c_j_huang@umc.com
Presentation: Presentation???? |
Abstract A new 0.25 µm flash EEPROM developed for embedded applications will be reported. Flash memory is achieved by utilizing a single transistor NOR type cell that employs Fowler-Nordheim tunneling for both program and erase operations. Channel FN tunneling is a high efficiency and low power consumption approach for flash cell operation. The flash EEPROM is integrated into a standard quarter micron logic process with dual gate oxide for high performance and high voltage transistors. Program and erase could be achieved within 5 ms to target. The high performance logic devices didn’t be degraded by incorporated with flash process was demonstrated. |
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Implementation of Self-Align Local Poly
Interconnection on 0.25um Flash Memory C.H. Lee, C.H. Lin, H.H. Chen, Y.K. Sheu, WenChi Ting, Gary Hong Specialty Technology Division. United Microelectronic Corp. No. 3, Li-Hsin Rd. 2 Science-Based Industrial Park Hsinchu, Taiwan, ROC |
Abstract ETOX Flash technology, the self-aligned source module plays a critical role in minimizing cell size. For advanced Flash technology using the shallow-trench isolation (STI) scheme, however, it is difficult to form a stable source line. The Flash process in this experiment features an ETOX structure and with SIN spacer. Poly-Si (implanted poly) is used as the local interconnection material connecting the source line and was successfully implemented in the ETOX flash array in this paper. Keyword: ETOX, local interconnection, shallow trench isolation (STI) |
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Expectations of MRAM in comparison with other
non-volatile memory technologies K.-M.H. Lenssen, G.J.M. Dormans, and R. Cuppens Philips Research Laboratories kars-michiel.lenssen@philips.com do.dormans@philips.com roger.cuppens@philips.com Presentation: Presentation???? |
Abstract Magnetic Random Access Memory (MRAM) is often presented as the ideal, all-purpose solid-state memory of the future. Indeed, it is expected that MRAM may provide a combination of properties that at present are only found distributed over different types of memories (SRAM, EEPROM, Flash, DRAM, etc.). This is certainly a very attractive perspective; if two (or more) different memory technologies could be replaced by a single memory technology (c.q. MRAM), the development costs for a next generation of a product comprising embedded memory could decrease dramatically. However, for this to come true, it is important that the specifications of MRAM will not merely be a compromise, only suitable for certain niche markets, but that they will really be able to compete with the (future) state-of-the-art “conventional memories”. In order to obtain a better insight in this matter, we have looked at (expected) properties of different non-volatile memories for one and the same technology node (0.18 µm). From this, the weaknesses and strengths of MRAM have been identified. Special attention was paid to a comparison with ferro-electric RAM (FERAM), which seems to be the most competitive alternative memory technology. |
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Mechanisms of Protonic
Nonvolatile Memory Device P.J. Macfarlanea and R.E. Stahlbush Naval Research Laboratory pmacfarl@estd.nrl.navy.com
Presentation: Presentation???? |
Abstract A nonvolatile memory device based on protonic transport in oxides has been proposed.1 The mobile H+ ions are introduced into the SiO2 layer by annealing Si/SiO2/Si structures in H2 at temperatures greater than 500oC. This effect has only been observed for confined oxides that have been annealed at ˇÝ1100oC prior to the hydrogenation anneal. This includes buried oxides such as Unibond and SIMOX as well as thermal oxides annealed with a polysilicon cap. An applied field moves the charge within the oxide and the charge stops moving when the field is removed. In a memory device, the hydrogen-annealed oxide is the gate oxide and the position of the mobile charge is sensed by the shift of the I-V curve. Much is still not understood about the motion of the charge across the buried oxide. Previous work has assumed that H+ transport and the time it takes to traverse the oxide is governed by interactions within the bulk of the oxide. Based on parameters that affect the transport time, we conclude that H+ trapping and detrapping at the Si/SiO2 interface are more important than H+ interactions within the oxide bulk. These parameters include the applied field, the H+ concentration and the oxide thickness. One consequence is that projections of device write-time based on the previous assumptions of H+ transport mechanisms may be overly optimistic. |
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Chalcogenide-Based Non-Volatile Memory Technology J. Maimon (jmaimon@ovonyx.com) E. Spall (espall@ovonyx.com) Ovonyx, Inc. R. Quinn (robert.quinn@lmco.com) S. Schnur (steven.schnur@lmco.com) Lockheed Martin Federal Systems Presentation:
maimon_ovonyx.pdf |
Abstract Chalcogenide is a proven phase change material used in re-writeable CDs and DVDs. This material changes phases, reversibly and quickly, between an amorphous state that is dull in appearance and electrically high in resistance, and a polycrystalline state that is highly reflective and low in resistance. The application of this commercially proven technology to create dense, high-speed, non-volatile semiconductor memories is discussed. |
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Ultra-high density holographic memory module
with solid-state architecture Vladimir B. Markov MetroLaser Inc. vmarkov@metrolaserinc.com Presentation:
markov_metro_laser.pdf |
Abstract NASA’s terrestrial, space, and deep-space missions require technology that allows storing, retrieving, and processing a large volume of information. Holographic memory offers high-density data storage with parallel access and high throughput. Several methods exist for data multiplexing based on the fundamental principles of volume hologram selectivity. We recently demonstrated that a spatial (amplitude-phase) encoding of the reference wave (SERW) looks promising as a way to increase the storage density. The SERW hologram offers a method other than traditional methods of selectivity, such as spatial de-correlation between recorded and reconstruction fields. In this report we present the experimental results of the SERW-hologram memory module with solid-state architecture, which is of particular interest for space operations. |
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SOI Non-volatile Memory P. J. McMarr, R. K. Lawrence, H. L. Hughes and W. C. Jenkins Naval Research Laboratory hughes@estd.nrl.navy.mil Presentation:
mcmarr_soi.pdf
|
Abstract SIMOX silicon-on-insulator (SOI) substrates were implanted with silicon ions at doses of 5x1015 and 1x1016 ions/cm2 at 130 keV. At this energy, the majority of the silicon ions were implanted into the buried oxide of the SIMOX substrate. Silicon-oxide-silicon test structures were fabricated on these implanted substrates. Pointcontact transistor (PCT) measurements were performed on the test structures and initial threshold voltages determined. A stress voltage was then applied to the test structure for times ranging from 10 millisec to 100 sec. After removal of the stress voltage, PCT measurements were again performed. The threshold voltages shifted by significant and reproducible values. This stress-voltageinduced device switching response forms the basis for a new type of non-volatile SOI memory. The temperature stability of this switching was studied from –50 oC to +200 oC. In addition, the field and time dependence of the switching is also presented. |
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Implementation of Ferroelectric Memories for
Space Applications Stephen C. Philpy, Gary F. Derbenwick, David A. Kamp and Alan F. Isaacson Celis Semiconductor Corporation celis@celis-semi.com Presentation:
philpy_nvmtp00p1.pdf |
Abstract Ferroelectric random access semiconductor memories (FeRAMs) are an ideal nonvolatile solution for space applications. These memories have low power performance, high endurance and fast write times. By combining commercial ferroelectric memory technology with radiation hardened CMOS technology, nonvolatile semiconductor memories for space applications can be attained. Of the few radiation hardened semiconductor manufacturers, none have embraced the development of radiation hardened FeRAMs, due a limited commercial space market and funding limitations. Government funding may be necessary to assure the development of radiation hardened ferroelectric memories for space applications. |
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Characterization of a New EEPROM/Flash Memory Cell Ron Reedy, Jim Cable, Frank Wright, Hal Anthony & Chuck Tabbert Peregrine Semiconductor Corporation Presentation:
reedy_peregrine_30vg.pdf |
Abstract This paper discusses on-going work sponsored through the Defense Threat Reduction Agency (DTRA) SBIR program at Peregrine Semiconductor Corp to characterize the radiation and endurance performance characteristics of Peregrine’s patented PlusCell TM - a new non-volatile memory cell which utilizes a standard CMOS process on a silicon on insulator technology. |
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Radiation Issues and Applications of Floating Gate
Memories L. Z. Scheick, leif.scheick@jpl.nasa.gov D. N. Nguyen, duc.nguyen@jpl.nasa.gov Jet Propulsion Laboratory Presentation:
scheick_jpl.pdf |
Abstract The radiation effects that affect various systems that comprise floating gate memories are presented. The wear-out degradation results of unirradiated flash memories are compared to irradiated flash memories. The procedure analyzes the failure to write and erase caused by wear-out and degradation of internal charge pump circuits. A method is described for characterizing the radiation effects of the floating gate itself. The rate dependence, stopping power dependence, SEU susceptibility and applications of floating gate in radiation environment are presented. The ramifications for dosimetry and cell failure are discussed as well as for the long term use aspects of non-volatile memories. |
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All-Metal Magnetic RAM E.J. Torok and R. Spitzer IME Minneapolis Minnesota and Berkeley California Presentation:
spitzer_ime.pdf |
Abstract The factors that enter into the development of an all-metal, nonvolatile magnetic RAM, in which multilayer giant magnetoresistive films are used for all functions – storage, readout, and support electronics – are described. |
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Opportunities and Challenges for
Embedded Flash Memory Sohrab Kianian, skianian@ssti.com Silicon Storage Technology, Inc. David Sweetman, d-dsweetman@att.net Presentation: Presentation???? |
Abstract With advances in deep submicron CMOS technology, faster timing and more feature-rich integrated silicon devices are being used in consumer electronics advanced communication and networking systems, computers, servers, and virtually all other electronic systems. The demand for performance and functionality is ever increasing and a key component of that demand is the in-system nonvolatile alterability of both code and data. Larger operating and application codes as well as configuration and personalization codes are stored in various IC components, which require field upgrade capability. Various types of data require nonvolatility. With systems becoming increasing portable and smaller in size, various bulky mechanical elements, such as magnetic storage disks, are designed out and silicon programmable elements are being substituted for them. The silicon elements must continue to provide better reliability and an ability to operate in harsher environments than media that have mechanical movement. These trends have presented an opportunity for flash and embedded flash as never seen before. The question is whether embedded flash is ready to serve these demands and keep up with the projected increasing demands well into the future. |
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3-D Computer Simulation of Nano-crystal
Floating –Gate Flash Memory Devices Aaron Thean and Jean-Pierre Leburton Beckman Institute for Advanced Science and Technology University of Illinois vthean@uiuc.edu Michael Sadd Motorola Inc, Semiconductor Products Sector Presentation:
thean_univ_of_il.pdfi |
Abstract We present a detailed investigation of single-electron charging effects in silicon nanocrystal quantum- dots, taking into account the quantum-mechanical properties of the silicon bandstructure. We show that the retention and erase times resulting from differences in the quantum coupling between the channel states and the nanocrystal states of different geometries can differ by orders of magnitude. |
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