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IDT DPSRAM SEE Test 08/2001

Summary

DUT: IDT 70V3319S133PRF Dual Port SRAM; 128-pin TQFP package

SEL: Detected at LET(Si) of 43 MeV.cm2/mg and higher, none below.

JTAG Upsets: None detected.

SEU: Detected for both memory array and address counter register for all used LET values (15-53 43 MeV.cm2/mg)

For SEL runs, DUT ICC was monitored and recorded by test software; for runs where SEL was observed, ICC chart is included.

Most SEU runs utilized "static" aproach: DUT was loaded with selected data pattern (all 0s, all 1s, checkered, address), then exposed to the beam.  At the end of the run ( Fluence of 1.0E6 1/cm2for all SEU runs) DUT memory array content was read back and number of errors recorded.  Error was defined as mismatch of one or more bits in a 18-bit word.  In order to test Address Counter Register loading and/or reading of array while exposing DUT to the beam was used for a few runs.
 

Latchup chart: sel.gif


SEU chart:  seu.gif

Run K-number Vcc Ion LET(Si) Tilt Time Flux Fluence Pattern Upsets XSection LatchUp Icc Chart Comments
    (V)   (MeV.cm2/mg) (deg) (sec) (1/cm2/sec) (1/cm2)   (word) (cm2/word)      
                             
330 6401B1 3.3 Br-81 37.46 0 85.9 1.17E+05 1.00E+07 check     0   SEL Test
331 6401B2 3.3 Br-81 37.46 0 9.1 1.11E+05 1.02E+06 check 154450 5.80E-07 0   SEU Test
332 6401B3 3.3 Br-81 43.25 30 11.8 8.62E+04 1.02E+06 check 171726 6.43E-07 0   SEU Test
333 6401B4 3.3 Br-81 52.97 45 13.8 7.36E+04 1.02E+06 check 194586 7.31E-07 1   SEU Test
334 6401B5 3.3 Br-81 52.97 45 81.8 7.13E+04 5.83E+06       1 lan6401b5.jpg SEL Test
335 6401B6 3.3 Br-81 43.25 30 124 8.10E+04 1.00E+07       0   SEL Test
336 6401B7 2.5 Br-81 52.97 45 146 6.84E+04 1.00E+07       0   SEL Test
337 6401B8 3.3 Br-81 52.97 45 118 5.96E+04 7.03E+06       1 lan6401b8.jpg SEL Test
338 6401B9 3.3 Br-81 52.97 45 42.6 5.80E+04 2.47E+06       1 lan6401b9.jpg SEL Test
339 6401B10 3.3 Br-81 52.97 45 124 5.79E+04 7.20E+06       1 lan6401b10.jpg SEL Test
340 6401B11 3.3 Br-81 52.97 45 199 4.14E+04 8.22E+06       0   SEL Test
341 6401B12 3.3 Br-81 52.97 45 15.1 3.04E+04 4.61E+05       1 lan6401b12.jpg SEL Test
342 6401B13 3.3 Br-81 37.46 0 17.5 3.02E+02 5.27E+03           bad run
343 6401B14 3.3 Br-81 37.46 0 54.4 1.83E+04 9.95E+05 address 141867 5.44E-07 0   SEU Test
344 6401B15 3.3 Br-81 37.46 0 163 8.04E+02 1.31E+05           bad run
345 6401B16 3.3 Br-81 37.46 0 45.3 2.23E+04 1.01E+06 0s 154242 5.81E-07 0   SEU Test
346 6401B17 3.3 Br-81 37.46 0 43.1 2.33E+04 1.01E+06 1s 155763 5.91E-07 0   SEU Test
347 6402B1 3.3 Br-81 37.46 0 59.7 1.68E+04 1.00E+06 0s 153270 5.82E-07 0   SEU Test
348 6402B2 3.3 Br-81 37.46 0 47.4 2.12E+04 1.01E+06 1s 148677 5.64E-07 0   SEU Test
349 6402B3 3.3 Br-81 37.46 0 47.1 2.14E+04 1.01E+06           bad run
350 6402B4 2.5 Br-81 37.46 0 50.4 1.99E+04 1.00E+06 0s 159234 6.06E-07 0   SEU Test
351 6402B5 2.5 Br-81 37.46 0 52.7 1.93E+04 1.02E+06 1s 144214 5.42E-07 0   SEU Test
352 6402B6 3.3 Br-81 43.25 30 24.3 1.04E+05 2.53E+06       1 lan6402b6.jpg SEL Test
353 6402B7 3.3 Br-81 43.25 30 103 9.74E+04 1.00E+07       0   SEL Test
354 6402B8 3.3 Br-81 43.25 30 105 9.57E+04 1.00E+07       0   SEL Test
355 6402B9 3.3 Br-81 52.97 45 25.2 7.77E+04 1.96E+06       1 lan6402b9.jpg SEL Test
356 6402B10 3.3 Br-81 52.97 45 59.4 7.95E+04 4.73E+06       1 lan6402b10.jpg SEL Test
357 6402B11 3.3 Br-81 52.97 45 31.4 7.77E+04 2.44E+06       1 lan6402b11.jpg SEL Test
358 6402B12 3.3 Br-81 52.97 45 53 7.87E+04 4.17E+06       1 lan6402b12.jpg SEL Test
359 6402B13 3.3 Br-81 52.97 45 13.8 7.78E+04 1.08E+06       1 lan6402b13.jpg SEL Test
360 6402B14 2.5 Br-81 52.97 45 136 7.35E+04 1.00E+07       0   SEL Test
394 6401C1 3.3 Cl-35 15.47 0 10.1 1.01E+05 1.02E+06 0s 78654 2.93E-07 0   SEU Test
395 6401C2 3.3 Cl-35 15.47 0 8.5 1.20E+05 1.02E+06 1s 100558 3.77E-07 0   SEU Test
396 6401C3 3.3 Cl-35 15.47 0 10.4 9.75E+04 1.02E+06 address 89560 3.36E-07 0   SEU Test
397 6401C4 3.3 Cl-35 17.86 30 13.2 7.67E+04 1.01E+06 address 104055 3.93E-07 0   SEU Test
398 6401C5 3.3 Cl-35 17.86 30 12.6 8.06E+04 1.02E+06 0s 91528 3.44E-07 0   SEU Test
399 6401C6 3.3 Cl-35 17.86 30 12.5 8.12E+04 1.01E+06 1s 116160 4.37E-07 0   SEU Test
400 6401C7 3.3 Cl-35 21.88 45 15.6 6.49E+04 1.01E+06 1s 128809 4.85E-07 0   SEU Test
401 6401C8 3.3 Cl-35 21.88 45 15.5 6.51E+04 1.01E+06 0s 106699 4.04E-07 0   SEU Test
402 6401C9 3.3 Cl-35 21.88 45 13.5 7.54E+04 1.02E+06 address 119202 4.48E-07 0   SEU Test
403 6401C10 3.3 Cl-35 21.88 45 12.9 7.90E+04 1.02E+06 address     0   SEU Test

Important Note: As was stated above, due to limitations of test software, the numbers for SEUs are for "word" errors ( one upset was recorded if one or more bits in a 18-bit word were flipped).  However, a small sample of the data readback was stored for each run; a quick analysis shows that for all runs the ratio of "bit erros" to "word errors" is in the range from 1.2 to 1.5.  ( this ratio represents the average number of error bits for every word registered as error).

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Last Revised: January 09, 2002
Digital Engineering Institute
Web Grunt: Richard Katz