|
NASA Advisory NA-GSFC-2006-01 |
Summary In both FPGA and EEPROM device applications, the realization of past parts issues was delayed, since the failure rate was low. Failures in non-flight parts are not always treated with the same rigor as failures in flight qualified devices. Additionally, proprietary and stove-piped information barriers, along with a cultural resistance to discussing failures, prevent the user community from pooling their data collectively, observing trends, and “connecting the dots.” Together, this had led to delays in manufacturers improving their parts, processes, and software. NASA GSFC kindly requests other NASA and non-NASA programs and projects to share with the Advisory Technical Point of Contact (see block 13) all DPA and Failure Reports on FPGAs and non-volatile memory devices, from both flight and engineering model usage along with lessons learned that can benefit the community. Note that prior to dissemination on the NASA Office of Logic Design web site, appropriate care (i.e. deleting items such as contractor names) will be taken. |
|
EA-2005-EEE-12-A |
Summary 4 Mbit EEPROMs delivered and not tested properly. The programmability of every memory cell in the 4 Mbit EEPROMs have not been verified. Failures experienced on two different 4 Mbit EEPROM devices have been found during memory writing using page write mode. The failure appears as half-page that becomes un-programmable after few write cycles. As the test progressed more bits became stuck at 0 in the second half of the page. |
|
NASA Goddard Space Flight Center |
Abstract EEPROM devices are widely used in NASA and other military and aerospace digital electronics system. This meeting will consist of focused talks from design engineers, parts engineers, reliability and mission assurance engineers, and factory engineers with discussion. The intent is to share experiences and knowledge, promote awareness of issues with these devices, and disseminate preferred application practices, ranging from proper circuit design to error mitigation techniques to proper memory system architectures. |
|
June 23, 2005 |
DPA Number: 55335 Manufacturer: Atmel Lot/Date Code: 0415 Function: EEPROM: 1,048,576 x 1-bit Serial Memory Designed to Store Configuration Image for FPGAs |
|
June 2005 |
Summary: The UT28F256QL and UT28F256LVQL 256k PROMs (QL PROMs) are functionally equivalent replacement devices for the UT28F256 and UT28F256LV PROM. These devices are a complete redesign of the legacy PROM devices and are built on a state-of-the-art 5V 0.35µm CMOS process using RadHard-by-Design techniques. The QL PROM along with the QuickLogic ViaLinkTM non-volatile programming element have been designed, characterized and demonstrated to support a reliable QL PROM device post programming, with NO added conditioning. The QL PROM devices will be damaged if subjected to the legacy PROM post program conditioning (PPC). |
|
Report Date:01/19/2005 |
Summary: Destructive Physical Analysis (DPA) was conducted per
GSFC document “Plastic Encapsulated Microcircuit (PEM) Guidelines for
Screening and Qualification for Space Application”, except that
cross-section was done without dye penetrant. Glassivation integrity test
was not performed.
Result: The devices met the requirements of GSFC. Note: Fifteen parts, with three different date code, were received for DPA. The date code and serial number are addressed as under. Five parts with date code 0349 (Serial numbers are 586, 587, 588, 589 and 590). Five parts with date code 0431 (Serial numbers are 886, 887, 888, 889 and 890). Five parts with date code 0433 (Serial numbers are 286, 287, 288, 289 and 290). |
|
Jeffrey Namkung and Jagdish Patel |
Abstract This paper describes a case study quantifying reliability and endurance results of two FRAM nonvolatile memories. The need for reliability and endurance testing is vital to space applications where single event upsets (SEUs) can occur in memory and disrupt or disable a flight system. The method used to test the ferroelectric nonvolatile memory FRAM chips incorporates a XILINX XC4010E FPGA performing read/writes to the memory chips and a PC in tandem to record errors. This method is extremely low cost and comparable in test times to commercially available memory testers with high hourly rates. Technologies: RAMTRON FM24C04 and FM1808 |
|
January 19, 2005 |
Summary: Destructive Physical Analysis (DPA) was conducted per
GSFC document “Plastic Encapsulated Microcircuit (PEM) Guidelines for Screening
and Qualification for Space Application”, except that cross-section was done
without dye penetrant. Glassivation integrity test was not performed. The
devices met the requirements of GSFC.
NOTE: Fifteen parts, with three different date code, were received for DPA. |
|
Saab Ericsson Space |
Background In the frame of a project several problems related to the EEPROMs have been encountered. Since several manufacturers are using the same die in the devices these problems are also relevant to them. The purpose of this document is to describe the encountered problems, symptoms and suggest a safe design methodology concerning the usage of EEPROMs in digital designs. |
|
November 5, 2003 |
Summary This memo documents the work of an independent team tasked to provide a probability of failure/success for bits in the boot code area of the RAD 6000 EEPROM. The analysis is based on the failing bit population for systems tested on the ground and in flight. Recommendations are provided to screen possible weak EEPROM bits. |
|
Aerospace Report No. TOR-2000(3000)-01 |
Synopsis Electrically Erasable Programmable Read-Only Memories (EEPROMs) can be used to store the initial boot or re-boot sequence in space systems. It it critical that these devices retain their memory flawlessly during the entire mission, especially in situations where on-board error correction and data refreshing options are limited. the part of interest is a 1 Megabit EEPROM produced by a commercial manufacturer and packaged by a separate vendor for space application. |
|
|
Synopsis This report represents the reliability test results on HITACHI 1Mbit EEPROM (HN58C1001 Series) using HITACHI's 0.8 µm CMOS design rule and HIACHI's standard wafer fabrication and assembly process. |
|
Contents Section 1: 1.1 Introduction; 1.2 Reliability: What is It?; 1.3 Failure Rates and Units of Measurement; 1.4 Bathtub Hazard Rate Curve; 1.5 Accelerated Testing Section 2 - Reliability Data: 2.1 Sample Selection; 2.2 Test Vehicles; 2.3 Life Test Data; 2.4 Qualification and Monitor Data Appendix A: A.1 Failure Rates and MTTF; A.2 Relationship Between FR and MTTF; A.3 Calculation of Observed FR and MTTF; A.4 Observed and Predicted Failure Rates; A.5 Predicted MTTF Appendix B - Extrapolating Failure Rates Using Arrhenius Equation: B.1 Calculation of Failure Rate and MTTF; B.2 Selection of Activation Energies Appendix C - Definitions |
|
|
June 1991 |
Introduction The family of EEPROM memories offered by SEEQ Technology ranges in size from 4K to 1,048Kbits. These products are manufactured using CMOS and NMOS wafer fabrication technologies. These memories are byte wide and conform to standard JEDEC configurations. The techniques used in process technology, circuit design, and testing methodologies are developed specially to provide high reliability product to our customers. The techniques include the use of redundant tunnel dielectric areas in the memory cell, an oxynitride process in the tunnel dielectric area for high endurance/low failure rate applications, and built-in special test modes for assurance of reliable memory cell operation. The SEEQ Reliability Program has been developed to determine the specific failure rates and failure mechanisms of the EEPROM memories. This data base includes the results from MIL-STD-883/Method 5005 testing, a product monitor sampling plan designed to complement (and supplement) the Military qualification activity, the initial qualification results for new die and packages, and the results of revalidation testing from critical changes to die or packages. The Arrhenius model is used to analyze the data and convert stress conditions to conditions that better represent those found in most operating systems. |
| Summary and Conclusion EEPROM technology-based devices are attractive components since they are both rewritable and non-volatile. Many of the products used in civil space systems are based on the Hitachi 1 Mbit commercial die. They are packaged by various vendors into either single chip packages or multi-chip modules. Bit failures, in two distinct EEPROM die, were reported on a flight instrument in the first year and a half of flight, with the initial analysis concluding that these were due to random defects. The analysis, however, could not be supported and a wider survey of EEPROM usage was conducted by various NASA Centers and contractors. It has been found that there have been a number failures ranging from single bit to page loss. The number of failures relative to the small sample size causes serious concern. |
|
1995 |
PART HISTORY: The subject part was noted to fail in the flight hardware during ambient testing. It was reported that the failures were seen during the PROM read/write test. Some failures occurred after a successful write. All failures occurred within a small range of addresses in a single part (the subject part). The failure caused the address being accessed to always have 0's in the data. |
June 3, 2003 |
Overview A number of EEPROM single bit and page failures were reported in space community, such as the half-page failure on Cassini and sub-page failures during EEPROM life test. Therefore, understanding the reliability and failure mechanisms of the EEPROM is critical to its space applications. This report summarizes the investigation of the EEPROM single bit failures that were observed on the Genesis Flight computer in flight during one year of operation, the single bit failure and page failure on Mars Exploration Rover non-volatile memory board (MER NVM_CAM) breadboard, the page failure during MER pre-launch testing of the RAD6000 flight unit, and the single bit failure on Deep Impact. Section I describes the EEPROM single bit failures observed on Genesis, MER and Deep Impact, page failures on MER, along with the traveler information. Section II provides a statistical reliability analysis of the EEPROM bit failures under different operating temperatures based on the Maxwell’s 1Mb EEPROM data sheet and reliability report. Section III gives a detailed investigation on weak cells at the chip and board level, performed on a virgin 1Mb EEPROM die, a MER die with a page failure, a MER die with a single bit failure and a Deep Impact die with a single bit failure. Summary of this investigation and recommendations are included in section IV. |
March 26, 2002 |
Introduction One sample lot consisting of three (3) randomly selected devices, part number AS8ER128K32Q, was received for Destructive Physical Analysis (DPA) testing in accordance with S-311-M-70 SEC. 5.12.3, MIL-STD-883 METHOD 5009, BALL DWG. 555492 and applicable Military Standards. LOT SUMMARY/CONCLUSION |
| HX6256_ttl_notice | Abstract The 256K SRAM in the 28 lead flat pack does not provide a satisfactory ground connection for operation in TTL mode for the Read conditions listed in datasheet HX6256. Toggling the NOE pin coincident with an address change could cause the chip to enter oscillation if all of the inputs are toggled together. (3/15/2002) |
| Call For Failures: Programmable Device Reliability - NEW!! | While the reliability of programmable logic devices is quite good, they do have a measurable failure rate. A database of device failures is being established. This will enable us to measure field reliability, categorize the failure modes, and spot trends as early as possible. |
| Flash_Burnin.pdf | Report on the Burnin of Intel Flash Memory Devices - DA28F016SV. |
| IntelFlash_Construction.pdf | Construction Analysis on Intel Flash Memory Devices - DA28F016SV. |
| UTMC_PROM_July_99.pdf | Accelerated Life Test Data for UTMC PROMs. (February 14, 2001) |
| FM1608_Reliability_Summary.PDF | Ramtron FM1608 Reliability Summary, March 30, 2000 (February 15, 2001) |
| FRAM_Reliability_Overview_June_2000.pdf | Ramtron Quality and Reliability Summary, June 2000 (February 15, 2001) |
| Low_Density_Reliability_Summary.pdf | Ramtron Serial Memory Reliability Summary, August 2000 (February 15, 2001) |
Home - NASA
Office of Logic Design
Last Revised:
January 12, 2006
Digital Engineering
Institute
Web Grunt: Richard
Katz
