NASA Office of Logic Design

NASA Office of Logic Design

A scientific study of the problems of digital engineering for space flight systems,
with a view to their practical solution.

Memory Papers
(ok, just building this up now, other papers are spread around)

 

Title, Authors, Reference, Link Abstract, Summary, Conclusions


Reliability Issues in Advanced CMOS Technologies: From Electrical Stresses to Radiation Damage

Alessandro Paccagnella
EWRHE, Villlard de Lans, 31 March 2004
ewrhe_paccagnella_2004.ppt

Outline

  • Introduction
  • Floating Gate (FG) memories: Flash memories
    • SEE and data retention
    • TID and endurance
  • Stressing the gate oxides
  • Plasma damage
  • Final considerations

Observations on the Reliability of COTS-Device-Based Solid State Data Recorders Operating in Low-Earth Orbit

C.I. Underwood and M.K. OldField
IEEE Trans. on Nucl. Sci.,  Vol. 47, No. 3
June 2000
pp. 647-653
underwood_2000.pdf

Abstract
This paper presents the results of Surrey Space Centre's experience in using different coding schemes and hardware configurations to protect data and software stored in COTS-device based memories on-board operational spacecraft in low Earth orbit.

Proceedings of the 2002 Nonvolatile Memory Technology Symposim

Coming soon ....

Proceedings of the 2002 Nonvolatile Memory Technology Symposim

program.htm

Proceedings of the 2001 Nonvolatile Memory Technology Symposim

nvmts_2001.htm

Proceedings of the 2000 Nonvolatile Memory Technology Symposim

nvmts_2000.htm

Storage Matrix

Wen Tsing Chow
US Patent 3,028,659
April 10, 1962

prom_patent.pdf

Excerpt:
In order to provide for field reliability, flexibility and possible remote preparation of matrices, the present invention proposes to prepare a matrix having an electrical element at each cross-over point in the laboratory or shop and then to remove unwanted elements in the field by physically disconnecting or electrically burning out the unwanted elements. The improved reliability stems from the fact that each connection can be made and inspected under shop conditions. The flexibility is afforded by the speed at which new constant boards can be prepared by "blowing out" certain connections, and is of particular value where certain data becomes available just prior to the start of calculations. The remote setting is made possible by providing connections from a control station to the matrix boards in order to burn out the undesired elements at the remote location. These connections may be by electical cables or conceivably by wireless means.

[Yes, this is the PROM]


SEE and TID Extension Testing of the Xilinx XQR18V04 4Mbit Radiation Hardened Configuration PROM

Carl Carmichael1 , Joe Fabula1, Candice Yui2, and Gary Swift2

1Xilinx Inc., San Jose, CA
2Jet Propulsion Laboratory, California Institute of Technology, Pasadena, CA

Presented at the 2002 MAPLD International Conference, Laurel, MD, September 10-12, 2002.

p21_carmichael_p.pdf (Paper)
p21_carmichael_s.ppt (Poster)

 Abstract
The XQR18V04 was evaluated for single event upset rates using proton and heavy ions. The PROM was demonstrated to be immune to latch-up, as well as to static upset in the flash memory cells, to an LET > 125 MeV/mg/cm 2 (effective). The PROM was also tested in a dynamic mode, which revealed three distinct error modes: Read Bit Errors, Address Errors, and a Single Event Functional Interrupt (SEFI) which affected the data output drivers. Saturation cross-sections, and onset thresholds, for these error modes were measured at the heavy ion facility at Texas A&M University, and the proton facility at UC Davis. Additional testing was performed at UC Davis and the Cobalt 60 source at McClellan Air Force Base to examine the effect to TID life as a function of power biasing. The PROM demonstrated a 100% improvement in total TID life with an 84% percent decrease in device usage.


Reliability Analysis of Programmed UTMC PROMs Following Post-Program Conditioning

Joseph M. Benedetto
1998 MAPLD International Conference
Greenbelt, MD, September 1998

pcd6.htm

Abstract
     Life test data were obtained on the UTMC Microelectronic Systems 64K and 256KBit programmable read-only memories (PROMs) following post-program conditioning (PPC). PPC is used to enhance the reliability (and radiation tolerance) of the UTMC PROMs following programming. To date, the life-test data show a mean time to failure (MTTF) for the 64K PROM of 1,476 years and a MTTF of 369 years for the 256K PROM (using a 60% confidence limit at 55° C). Data collection is continuing and updated reliability numbers will be published, as they become available.
     The UTMC Microelectronic Systems (UTMC) 64K and 256K programmable read-only memory (PROM) uses an amorphous silicon (a -Si) based antifuse. In the unprogrammed state the antifuse has a high resistance, typically >109W . Following programming with a series of voltage pulses, a low resistance filament is created. The UTMC PROMs use a 2-transistor/2-antifuse structure for each cell. Following programming, each cell has one programmed (low-resistance) antifuse and one unprogrammed (high-resistance) antifuse. For reliable operation, therefore, the programmed antifuse must stay in a low resistance state and the unprogrammed antifuse must stay in a high resistance state for the life of the product.
    The reliability of the unprogrammed antifuse structures were determined through a design of experiments (DOE) approach which used accelerated voltage stressing to calculate a failure rate. To determine the reliability of the programmed antifuse a thermally activated test method was used. PROMs were programmed with an "AA55" pattern (considered a worst case test pattern for these devices), conditioned with 64 hours of unbiased bake followed by 64 hours of voltage stressing. The combination of unbiased bake and voltage stressing following programming is called post-programming conditioning (PPC). The conditioned PROMs were then subjected to an extended life test at 150° C with a 5.5V dynamic stress pattern. The details of the PPC followed by the life-test results are discussed in the final paper


Backside Device Irradiation for Single Event Upset Tests of Advanced Devices

Gary M. Swift
JPL/California Institute of Technology

Thirteenth Biennial Single Effects Symposium
Manhattan Beach, CA, April, 2002

swift_thin_seesymp02.ppt

Tales from the Cave

  • Texas A&M Wishlist:
    • Upstream Degrader (for uniformity)
    • LET and/or Energy Spectrum Detector
  • Backside thinning is NOT so easy
    • Yield Problems
    • Need Long-Range Ions
  • Backside Irradiation Requires Careful LET Assignments

Examples include SDRAMs and the Power PC (May 7, 2002)


An Error Correction Code to Address Neutron Single Event Upsets in Semiconductor Memory

David W. Jensen, Ph.D.
Advanced Computing Systems
Rockwell Collins

Thirteenth Biennial Single Effects Symposium
Manhattan Beach, CA, April, 2002
jensen_rockwell_seesymp02.ppt


Introduction and Summary

  • Why concerned about Neutron Single Event Upsets (NSEUs)?
  • Error correction codes
  • Combining multiple mitigation techniques could enable an NSEU-tolerant, commercially-fabricated microprocessor

  • Presented efficient error correction block code to address Singe Event Upsets (SEUs) and Multiple Bit Upsets (MBUs) in semiconductor memory

Note: Could not make a .pdf file.  (May 3, 2002)


SDRAMs: Can’t Live Without Them, But Can We Live With Them?

Ray Ladbury GSFC/Orbital
Munir Shoga BSS
Rocky Koga Aerospace Corp.

Thirteenth Biennial Single Effects Symposium
Manhattan Beach, CA, April, 2002
sdram_seesymp02.ppt


Single-Event Effects in SDRAMs can be a nightmare!!

  • Single-Event Latchup (SEL)--potentially destructive--at best, results in loss of all data stored on chip.
  • Single-Event Upset (SEU)--can occur at at rate of several per day and multi-bit upsets a few times per day per chip.
  • Single-Event Functional Interrupt (SEFI)--results in loss of chip functionality; power cycle (causing loss of all data on the chip) is usually necessary for recovery.
  • Stuck Bits--can cause temporary or permanent loss of functionality of a single-bit, impairing reliability and error detection performance.
  • Some experimenters have seen error/failure rates vary more than 10x lot to lot.

Note: Could not make a .pdf file.  (May 2, 2002)


SEE and TID of Emerging Non-Volatile Memories

D. N. Nguyen, L. S. Scheick
Jet Propulsion Laboratory

Presented at the 2002 IEEE NSREC
Phoenix, AZ

 Abstract
We report on the SEE and T D tests of higher density flash memories. Both normal and irregular SEFI were observed, indicating upsets from complex control circuitry.  TID results are compared with tests from previous generations.

 


32Kx8 PROM Radiation Test Results

Scott Doyle and Ron Brown
Lockheed Martin Federal Systems
Manassas, Virginia 20110

1997 Digest of Papers
Government Microcircuit Applications Conference (GOMAC)

 

 Abstract
A radiation hardened 32Kx8 PROM is available with radiation immunity to single event effects (SEE) including single event upset (SEU), single event dielectric rupture (SEDR), and latchup (SEL).  total ionizing dose (TID) levels greater than 200 krads are guaranteed.  Radiation hardness was achieved through a combination of process and design enhancements.  QML qualification has been received.  The radiation test data and results are presented.

Radiation Hardened Memories for Space Applications

Nadim F. Haddad, Ronald D. Brown, Scott Doyle and Steven J. Wright
BAE SYSTEMS
9300 Wellington Road, Manassas, VA 20110 USA
703-367-5251
nadim.haddad@baesystems.com

IEEE Aerospace Conference, 2001

 Abstract
Several generations of radiation hardened memory products were developed to support space applications. Both process technology enhancements and specialized design techniques were used to overcome the weaknesses of commercial memories when used in the space environment. The natural advancement of semiconductor technology was used to progressively increase density, enhance performance, and reduce power consumption.

Historically, radiation hardened memories for space were fabricated at specialized foundries to achieve strategic levels of radiation hardness for both natural space and military applications. The demand for higher densities and lower cost, however, are pushing for design compatibility with state-of-the-art commercial foundries for 4M SRAM and beyond, and creating a new set of products targeting natural space. Advanced packaging technology is used to improve bit density and reduce weight, both of which are critical for space missions.

TABLE OF CONTENTS

1. INTRODUCTION
2. WEAKNESSES OF COMMERCIAL MEMORY IN SPACE
3. RADIATION HARDENING FEATURES OF SPACE MEMORIES
4. ROAD MAP OF SPACE HARDENED MEMORIES
5. PACKAGING FOR SPACE MEMORIES
6. RADIATION CHARACTERIZATION
7. Conclusion

Radiation Hardened Memory Development at Honeywell

Hassan Kaakani
Honeywell Solid State Electronics Center

IEEE Aerospace Conference, 2001

 Abstract
Deep submicron Silicon on Insulator (SOI) technology advancements at Honeywell have enabled new generations of radiation hard memory products. This paper will cover plans and results of our SOI technology development programs for SRAM products and Giant Magneto Resistive (GMR) non-volatile memory.

TABLE OF CONTENTS

1. INTRODUCTION
2. SRAM PRODUCT DEVELOPMENT - 1M, 4M, 16M, AND SRAM ROADMAP
3. GMRAM TECHNOLOGY
4. NONVOLATILE MEMORY COMPARISONS
5. GMRAM ADVANTAGES AND APPLICATIONS
6. GMRAM PRODUCT DEVELOPMENT
7. CONCLUSIONS


SONOS Nonvolatile Semiconductor Memories for Space and Military Applications

Dennis  A. Adams1, David Mavis2, James R. Murray3, and Marvin H. White4

1Northrop Grumman Corp.
2Mission Research Corp.
3Sandia National Labs
4Lehigh University

dennis_a_adams@md.northgrum.com
dgmavis@rt66.com
jrmurra@sandia.gov
mhw0@lehigh.edu

IEEE Aerospace Conference, 2001

 Abstract
Silicon-Oxide-Nitride-Oxide-Silicon (SONOS) based nonvolatile memory has emerged as the most mature nonvolatile semiconductor memory (NVSM) currently in use for space applications.  SONOS 64k EEPROMs have been flying in numerous satellite applications since 1992 with a 256k EEPROM version of this part qualified for space applications in 2000.  This paper will summarize the production and development status of a family of SONOS-based devices (EEPROMs, FPGAs, Controller ASICs) currently being manufactured at the Northrop Grumman Corporation (NGC) Advanced Technology Laboratories in Baltimore, Maryland.

Note: MAPLD referenced in the paper.


Chalcogenide-Based Non-Volatile Memory Technology

Jon Maimon1
Ed Spall1
Robert Quinn2
Steven Schnur2

1Ovonyx, Inc.
2BAE Systems

jmaimon@ovonyx.com
espall@ovonyx.com
robert.quinn@lmco.com
steven.schnur@lmco.com

IEEE Aerospace Conference, 2001

 Abstract
Chalcogenide is a proven phase change material used in re-writeable CDs and DVDs.   This material changes phases, reversibly and quickly, between an amorphous state that is dull in appearance and electrically high in resistance, and a polycrystalline state that is highly reflective and low in resistance.  The application of this commercially proven technology to create semiconductor memories is discussed.  The successful results of an effort to create a memory cell that would allow for the production of a dense, low power, non-volatile memory is presented.

Table of Contents

  1. Introduction
  2. Chalcogenide Technology: CD-RW and DVD-RAM
  3. Chalcogenide Technology: Semiconductor Memories
  4. Current Program Description
  5. Results to Date
  6. Conclusions


SEU and SEL Response of the Westinghouse 64K E2PROM, Analog Devices AD7876 12-Bit ADC, and the Intel 82527 Serial Communications Controller

Sexton, F.W.; Hash, G.L.; Connors, M.P.; Murray, J.R.; Schwank, J.R.; Wlnokur, P.S.; Bradley, E.G.
Radiation Effects Data Workshop, 1994 IEEE, pp. 55 -63

 Abstract (excerpt)
The Westinghouse SA3823 64K E2PROM radiation-hardened SONOS non-volatile memory exhibited a single-event-upset (SEU) threshold in the read mode of 60 MeV-cm2/mg and 40 MeV-cm2/mg for data latch errors.  The minimum threshold for address latch errors was 35 MeV-cm2/mg.  Hard errors were observed with Kr at VP = 8.5V and with Xe at programming voltages (VP) as low as 7.5 V.  No hard errors were observed with Cu at any angle up to VP=11V.   The system specification of no hard errors for Ar ions or lighter was exceeded.   No single-event latchup (SEL) was observed in these devices for the conditions examined.
256k_eeprom_presentation.pdf 256K EEPROM Status, SMDC High Performance Microelectronics TIM, May 26, 1999.   Northrop-Grumman.

32K X 8 Radiation-Hardened CMOS/SONOS EEPROM

256k_eeprom.pdf

 Abstract
     A 32K X 8 radiation tolerant CMOS/SONOS EEPROM is described. The technology is a 1.2 micrometer radiation tolerant CMOS process into which is incorporated an oxide-nitride-oxide nonvolatile memory dielectric. This ONO dielectric when used as the gate dielectric of an n channel MOSFET, forms the variable threshold transistor which is the basis for the EEPROM. Charge is stored by tunneling into traps in the nitride, rather than on a floating gate as is done with most EEPROMs. No hot electron effects are used for programming or erase, so programming and erase power dissipation are quite low. Circuit design was done at Sandia National Labs and device fabrication is done by Northrop Grumman Corporation.

Home - NASA Office of Logic Design
Last Revised: April 08, 2004
Digital Engineering Institute
Web Grunt: Richard Katz
NACA Seal