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Conclusion A combinational EDAC circuit can provide error detection and correction capabilities against static errors. Proper analysis must be conducted for dynamic errors such as signals that oscillate or have non-logic levels. |
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NASA Public Lessons Learned System (PLLS) Database |
Abstract: Shortly after the commencement of science activities on Mars, an MER rover lost the ability to execute any task that requested memory from the flight computer. The cause was incorrect configuration parameters in two operating system software modules that control the storage of files in system memory and flash memory. Seven recommendations cover enforcing design guidelines for COTS software, verifying assumptions about software behavior, maintaining a list of lower priority action items, testing flight software internal functions, creating a comprehensive suite of tests and automated analysis tools, providing downlinked data on system resources, and avoiding the problematic file system and complex directory structure. |
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LUNA-C DD3 16M (4Mx4) DRAM with On-Chip ECC |
Summary Signal integrity is important for all devices, of course and it is noted that signal integrity requirements are usually treated as an aside, even by the manufacturers, as well as the user. However, many DRAM and SDRAM manufacturers make signal integrity requirements very prominent and explicit -- this is not done to make their parts harder to use! IBM has carefully specified requirements for their 16 Mbit DRAM and the key figures and text is presented below as one specific example. As always, consult specific data sheets and application notes for each particular design. |
| HX6256_ttl_notice | Abstract The 256K SRAM in the 28 lead flat pack does not provide a satisfactory ground connection for operation in TTL mode for the Read conditions listed in datasheet HX6256. Toggling the NOE pin coincident with an address change could cause the chip to enter oscillation if all of the inputs are toggled together. (3/15/2002) |
| Ramtron_Reliability_0699.pdf | Ramtron 16 kb Reliability Summary - June, 1999. |
| papers.htm and presentations.htm | Please see the collection of papers and presentations for more application notes and device test results. |
| UTMC_PROM_Appnote.pdf | Summary—Life test data were obtained on the UTMC Microelectronic Systems 64K and 256KBit programmable read-only memories (PROMs) following post-program conditioning (PPC). PPC is used to enhance the reliability (and radiation tolerance) of the UTMC PROMs following programming. To date, the life-test data show a mean time to failure (MTTF) for the 64K PROM of 1,476 years and a MTTF of 369 years for the 256K PROM (using a 60% confidence limit at 55°C). Data collection is continuing and updated reliability numbers will be published, as they become available. |
| 256k_eeprom_presentation.pdf | 256K EEPROM Status, SMDC High Performance Microelectronics TIM, May 26, 1999. Northrop-Grumman. |
| FRAM_Images.htm | Image of FRAM devices, ready for test. |
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December 21, 2005
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Richard Katz
