SEU Mitigation Design Techniques for Radiation-Hardened Virtex Series FPGAs

Carl Carmichael
Xilinx Corporation

The functionality of a design implemented in an SRAM-based Programmable
Logic Device (eg FPGA) exhibits some level of susceptibilty to SEU upsets. A common SEU 
mitigation technique is to place "triple redundancy with voting" into the critical
logical paths within a design. However, in a programmable device the voter
circuit would also be susceptible to SEUs. This may make these devices not suitable for
certain space applications.

This paper presents a simple but highly effective voter circuit for the Xilinx Virtex 
series FPGA architecture in which the susceptibilty to SEUs is mitigated, thereby 
allowing the use of Virtex series FPGAs in more mission critical applications.