PROGRAMMABLE TECHNOLOGIES WEB SITE

A scientific study of the problems of digital engineering for space flight systems,
with a view to their practical solution.

Preliminary Program

1998 Military and Aerospace Applications of

Programmable Devices and Technologies Conference

(MAPLD Conference)

Preliminary Program by Author

(in Alphabetical Order)

B6: Peter Alfke and Rick Padovani
Xilinx Corp.

"Radiation Tolerance of High-Density FPGAs"

SRAM-based high-density FPGAs offer many advantages in satellite and other aerospace applications: High level of integration to greater than 100,000 system gates, no NRE, low power consumption, and - most important- the ability to be reconfigured in the operating system, allowing system upgrades in space.
A perceived drawback is the susceptibility of configuration latches to radiation-induced upsets.

Heavy-ion testing at Brookhaven have established that the specially processed Xilinx XQR4000XL-family devices exhibited latch-up immunity at LET > 100 MeV*cm2/mg at 125 degrees C. These test also showed a very low probability of soft errors in their configuration-storage latches and user flip-flops. Also, neutron tests performed in Scandinavia show excellent results.

Xilinx FPGAs offer a unique “readback” capability that can monitor all storage cells on the chip without interfering with the operation of the device in the system. This makes it possible to build triple-redundant systems that can detect and repair a soft error within a fraction of a second, and thus avoid any accumulation of errors.

A4: Raymond J. Andraka, P.E and Dr Richard Phelps
Andraka Consulting Group, Inc and Telephonics

"An FPGA based processor yields a real time high fidelity radar environment simulator."

Radar parametric testing has traditionally required either expensive trials in real-world situations (with many uncontrolled variables) or very limited 'canned' tests. The Von Neumann processors normally used for signal processing are severely limited in this application because of the inherently serial instruction stream. This paper discusses the use of FPGAs to accelerate the processing to obtain a near real time environment simulator. The FPGA logic handles the time-sensitive tasks such as target sorting, waveform generation, sea clutter modeling and noise generation. DSP microprocessors handle the less critical tasks like target movement and radar platform motion. The result is a simulator that simultaneously produces several hundred independent moving targets, realistic sea clutter, land masses, weather, jammers and receiver noise.

PAB8: Jeffery Banker
Pico Technology, Inc.

"Quick-Turn MCMs in a 3-D Stack"

    Technology for a 3-D stack of MCMs has been developed to significantly reduce the size of spacecraft systems and subsystems. The critical enhancement offered by the 3-D approach is the integration of a quick-turn, programmable multichip module substrate technology within the MCM stack. This highly integrated electronic packaging concept will support various critical applications such as Command and Data Handling (C&DH), volatile and nonvolatile memory subsystems, and complex science experiments. The programmable substrates will allow rapid, low-cost integration of these custom functions within 3-D stacks in spacecraft, aircraft, or ground vehicles.

PCD6: Joseph M. Benedetto
UTMC Microelectronic Systems, Principal Reliability Engineer

"Reliability Analysis of Programmed UTMC PROMs Following Post-Program Conditioning"

Life test data were obtained on the UTMC Microelectronic Systems 64K and 256KBit programmable read-only memories (PROMs) following post-program conditioning (PPC). PPC is used to enhance the reliability (and radiation tolerance) of the UTMC PROMs following programming. To date, the life-test data show a mean time to failure (MTTF) for the 64K PROM of 1,476 years and a MTTF of 369 years for the 256K PROM (using a 60% confidence limit at 55° C). Data collection is continuing and updated reliability numbers will be published, as they become available.

    The UTMC Microelectronic Systems (UTMC) 64K and 256K programmable read-only memory (PROM) uses an amorphous silicon (a -Si) based antifuse. In the unprogrammed state the antifuse has a high resistance, typically >10^9W . Following programming with a series of voltage pulses, a low resistance filament is created. The UTMC PROMs use a 2-transistor/2-antifuse structure for each cell. Following programming, each cell has one programmed (low-resistance) antifuse and one unprogrammed (high-resistance) antifuse. For reliable operation, therefore, the programmed antifuse must stay in a low resistance state and the unprogrammed antifuse must stay in a high resistance state for the life of the product.
    The reliability of the unprogrammed antifuse structures were determined through a design of experiments (DOE) approach which used accelerated voltage stressing to calculate a failure rate. To determine the reliability of the programmed antifuse a thermally activated test method was used. PROMs were programmed with an "AA55" pattern (considered a worst case test pattern for these devices), conditioned with 64 hours of unbiased bake followed by 64 hours of voltage stressing. The combination of unbiased bake and voltage stressing following programming is called post-programming conditioning (PPC). The conditioned PROMs were then subjected to an extended life test at 150° C with a 5.5V dynamic stress pattern. The details of the PPC followed by the life-test results are discussed in the final paper

PCD1: Neil W. Bergmann and Peter R. Sutton
Cooperative Research Centre for Satellite Systems, Queensland University of Technology, Brisbane Australia

"A High-Performance Computing Module for a Low Earth Orbit Satellite using Reconfigurable Logic"

A combination of FPGAs and conventional processors (DSPs and/or mi in a high performance computing module which will be used to enhance the performance of an Australian low-earth orbit satellite, FedScroprocessors) are usedat-1, which will be operational in 2001. The high performance computer will provide additional hardware redundancy, on-board data processing, data filtering and data compression for science data, as well as allowing experiments in dynamic reconfigurability of satellite computing hardware in space.  The paper will describe the payload, as well as examine the benefits of using reconfigurable logic, both from the satellite engineering aspects (eg. flexibility to make late reconfigurable circuit changes) and the satellite performance aspects (improved mission outcomes).

B3: Joseph B. Bernstein
University of Maryland Reliability

"Laser Programmable Interconnections Between Metal Lines"

    Solid metallic connections have been successfully formed between two standard levels of metalization using focussed IR laser pulses. This process of laser formed connections has been used to link continuous chains with resistances of less than 0.8ohm per connection. A commercial laser repair system used extensively by the memory industry was employed to perform individual links without failures in 100,000's of attempts. This technology has the potential to replace laser fuse cutting and voltage programmable interconnect techniques to implement repair schemes and it is being used to program wiring in MCM-D and wafer scale integration applications on silicon substrates. Furthermore, because it is an additive process, it lends itself to redundancy for higher yield and reliability.

The principle of link formation depends on material properties of the metallization system. Metal is plastic, has a low melting point, and is encased by dielectric. A lower metal layer will absorb focussed laser energy that is transmitted through the oxide and nitride and expand within the time scale of a Q-switched laser pulse. However, brittle dielectric will not be able to support the rapid expansion without fracturing. Once a fracture is initiated, the molten metal expands to flow through the resulting crack and fills the void. The resulting connection is a solid metallic via whose reliability is electromigration limited with sub-Ohmic resistance and is more robust than any alternate programmable substrate technology.

A1: Joe Bogdanski
APL

"Space Qualified Large Memory Array Implementation for a Solid State Recorder"

This talk chronicles the design of a solid state recorder (SSR). The SSR’s design was developed for the Goddard supported Command and Data Handling In your Palm project. The design was later modified and used for the TIMED satellite. Commercial parts, principally DRAM and FPGAs which are susceptible to single event upset (SEU) from protons or heavy ion particles, dramatically influenced the SSR’s design. Techniques for detecting and correcting SEUs in sensitive parts were extensively used, these included block error codes on data and voting hardware logic.

PAB6: Howard Bogrow
Xilinx, Inc

Field Programmable Gate Arrays (FPGAs) have become the technology of choice for many Military and Aerospace system designers. This is true for new system development as well as for upgrading/retrofitting existing systems. Because FPGAs are available as an off-the-shelf product, there is no longer the need to develop custom logic circuits. This provides the benefits to the designer of having access to components that greatly reduce development time and allow for design changes right up to the production phase, and also allow for field upgrades once the system is deployed. Re-programmable FPGAs can also be reconfigured on-the-fly to accommodate multiple system missions. Employing the concepts of “best commercial practices” has made high-density FPGAs, manufactured on state-of-the-art advanced processes available to the Mil/Aero designer.

PAB10: Morris Clark
Xanthon, Inc.

"Review of a Multi-processor PCI Board"

The powerful combination of a DSP with a parallel processing architecture of a symmetrical ring FPGAs has been developed to deliver a flexible, scalable processing engine, capable of handling demanding digital signal processing applications. The architecture was designed with the highest degree of performance, scalability and flexibility. There are six major elements to the architecture: symmetrical processing ring of 8 FPGAs, DSP, communication network, PCI subsystem, expansion connectors and daughtercard modules.

B5: B. Cronquist, M. Sarpa, J.J. Wang, and R. Katz, et., al.
Actel Corp. and NASA/GSFC

"Modifications of COTS FPGA Devices for Space Applications"

A review of the ongoing efforts to improve the applicability of standard CMOS COTS devices to space environments. Discussions will center on specific design and processing techniques that will include methods of increasing total dose survivability levels and decreasing single event upset susceptibility. These concepts were guided by observations and measurements made on the Actel OTP FPGAs through eight process generations (2.0um to 0.25um). Both one-time and reprogrammable FPGA futures will be reviewed.

A3: Grason Curtis
Synplicity

"Embedded Synthesis: A New Design Methodology for Deep-Submicron Programmable Logic Devices"

In the past three years, the programmable logic industry has experienced a dramatic shift in both density and complexity. As densities increased, new design methodologies were required. Schematic and equation based design entry worked for simple PLD’s and even low-density FPGA’s. But as PLD’s pushed above 10K gates, Hardware Description Languages (VHDL and Verilog) became necessary to satisfy decreasing design schedules. Synplicity introduced Synplify in 1994 as the first synthesis tool written from the ground up specifically for programmable logic optimization. As CPLD and FPGA’s continue to migrate down into deep-submicron geometry’s, a new design methodology again will be required. Issues prevalent in ASIC design: physical placement, routing delays, advanced timing optimization, intellectual property cores, etc. are now starting to be seen in the high density FPGA/CPLD design. To meet these new challenges, Synplicity introduced a new methodology called Embedded Synthesis: the linking of logic synthesis and physical design. This presentation will describe Embedded Synthesis and its impact on deep-submicron programmable logic design.

D2: Patrick W. Dowd, John T. McHenry, Todd M. Carrozzi, William B. Cocks, Frank A. Pellegrino
U.S. Department of Defense, University of Maryland

"Low-Cost Line Speed IP Packet Filtering in ATM Networks"

This presentation describes an IP-firewall capable of scaling to high data rates that enables a high degree of traffic selectability at a low cost. This firewall avoids the usual performance penalties associated with software implementations, and this approach is applicable to high-speed broadband networks. Its application to Asynchronous Transfer Mode (ATM) networks and IP over ATM networks is discussed in particular. The keys to this approach lie in an FPGA-based inline processor that is used in a hierarchical processing structure to enforce the security policy, and in its ability to register both approved and disapproved flows. The approach described in this paper allows approved connections to proceed at line speed with no performance degradation.

B1: Jon Ewald
QuickLogic Corporation

"Military-Temperature Plastic FPGAs Provide Same Security, Performance and Reliability as Ceramic FPGAs at Half the Cost"

As reduced military budgets drive the trend towards COT, designs that could previously only be addressed with higher-cost, ceramic-packaged FPGAs can
now be implemented with lower-cost, plastic-packaged parts. Members of QuickLogic's pASIC 1 and pASIC 3 families of plastic-packaged 5.0 or 3.3 volt devices, have been qualified and tested to operate over the industry standard military temperature range of -55° C to +125° C and offer users the same performance, security and reliability as ceramic-packaged military components. Featuring standby current consumption as low as 500uA resulting in standby power consumption of just 1.65mW, the plastic-packaged devices operate reliably at the extreme 125° C hot temperature specified for the industry-standard military-temperature range.

A2: Marco Figueiredo, Ken Winiecki, Terry Graessle, and Umesh Patel
NASA Goddard Space Flight Center

"Study of the Utilization of Adaptive Computing in Space Applications"

PCD10: Clay Gloster, Marco Figueiredo
Department of Electrical & Computer Engineering, NC State University,
SGT Inc. / NASA Goddard Space Flight Center

This poster presentation directly addresses the issues related to rapid prototyping of remote sensing science data processing applications using adaptive computers. Our results demonstrate that the use of the Java object-oriented programming language together with an adaptive computing platform significantly reduces development time, for a typical remote sensing application, while improving performance by an order of magnitude. An interesting result, obtained by executing a remote sensing science data processing application benchmark from a remote site demonstrates that a distributed adaptive computing implementation can be preferred over a traditional software implementation.

D3: Kazem Haji and Brad Brown
Southwest Research Institute

"A Reconfigurable Computing Platform for Detection and Direction Finding of Frequency Hopping Signals"

    SwRI is developing a reconfigurable computing platform for detection and direction finding (DF) of frequency hopping signals using COTS FPGA-based boards derived from NSA's SPLASH 2 technology. Concurrent DF engines process different sub-bands of the tuned spectrum as tasked by the detection alarms. The architecture supports wideband detection and DF processor functions. In the basic configuration, the DF processor is made up of eight FPGAs, six of which support the DF engines. The number of concurrent DF engines depends on the DF algorithm used, the optimization methodology (area vs. speed), and the capacity of the FPGA.

D6: David C. Hoffmeister(1,3) and Patrick W. Dowd (2,3)
1: Department of Electrical Engineering,
    State University of New York at Buffalo
2: National Security Agency, Fort Meade, MD
3: Department of Electrical Engineering, University of Maryland at College Park

"An FPGA-based Network Interface for WDM Gigabit Networks"

A network interface (NI) for wavelength-division multiplexed (WDM) gigabit networks is presented that is based on field programmable gate array (FPGA) technology. This NI is being used for Project Lightning, a dynamically reconfigurable WDM network testbed project for supercomputer interconnection. The NI is implemented using FPGAs to allow experimentation involving the media access protocol and reconfiguration control for Lightning. This reprogrammability will also allow the NI to be used as a general testbed platform for WDM gigabit networks. This work was supported by the U.S Department of Defense, Laboratory for Physical Sciences, College Park, Maryland.

D1: Brad L Hutchings
Brigham Young University, Hewlett Packard Laboratories, Ltd

TBA

    Configurable-computing researchers commonly resort to standard ASIC design tools when mapping applications to FPGAs. They have little choice. However, because these tools have been optimized for ASIC design, they often fall short when it comes to achieving high performance designs in FPGAs. When implementing high performance designs with FPGAs, it is usually quite important to control both the structure and flooplan to some degree. Unfortunately, current tools make this more difficult than it needs to be. For example, schematic capture is useful for controlling the low-level structure and placement of designs but is typically useless for creating the parameterized and reusable circuit blocks often found in configurable-computing applications. High-level synthesis tools on the other hand allow for the creation of parameterized designs but often don't provide the designer with sufficient control over the low-level details of a design. Combining these two tools tends to be the only way to achieve reasonable results but the process tends to be time consuming, frustrating, and error prone. In general, we are finding that the shortcomings of these tools hamper designer productivity and ultimately limit the level of performance you can achieve. This talk will discuss the JHDL project, currently underway at Brigham Young University, that seeks to develop a tool suite that overcomes some of the problems found in commercial tools. The tool suite is being developed in parallel with a set of applications and early results are already showing increased productivity. This talk will first introduce the topic by discussing what is unique to configurable-computing applications as opposed to ASIC design and will discuss the various elements of the tool suite, their current status and how they have been tailored specifically for development of configurable-computing applications.

PCD9: Karen Jefferson, Myong An, Alfredo R. Baeza, and Joseph C. Wehlburg.

Sandia National Laboratory

"Real Time Reconfiguarable Image Analysis"

    Sandia National Laboratories is prototyping a reconfigurable image processing system using FPGAs. Two algorithms that have application in
space collected imagery are being implemented. The first algorithm allows multiple frames from a staring sensor to be integrated into a single "superresolution" image by using information gained by subpixel shifts between frames. The second algorithm allows inversion of a sequence of chromotomographic data into an image cube of hyperspectral data. The principle is similar to the familiar CT scan used for medical purposes. These two algorithms have significant computational similarities, and this will be exploited in the reconfigurable system.

PCD11: Sanjaya Kumar

Honeywell

"Benchmarking Technology for Configurable Computing Systems"

    This poster presents benchmarking technology for assessing configurable computing systems. An important goal is to provide benchmarks that expose as much information as possible about a configurable computing system's infrastructure, revealing insights about tools and architectures. This effort is the first to specify a set of characteristics relevant to configurable computing (versatility, capacity, timing sensitivity, interfacing, and scalability), and is based on an unbiased and technology independent formal benchmark specification methodology. In addition, it addresses a broad range of configurable architectures, including single FPGA devices, multi-FPGA boards, fixed-plus-variable devices, and hybrid systems. The benchmarking technology allows users the ability to examine various trade-offs, refine their configurable computing platforms, and select appropriate configurable computing elements. Benchmarks based on the characteristics above are presented, along with a status of the effort.

PAB9: Miriam Leeser
Northeastern University, Dept. of Electrical and Computer Eng.

"Color and Spatial Clustering for Image Analysis with an FPGA-based Computing System"

    FPGA platforms are ideally suited for the initial processing of images for computer vision. The large amount of image data can be preprocessed by exploiting the inherent parallelism available in FPGA architectures and effectively keeping unnecessary amounts of data off the host processor. FPGA implementations can be specialized to the specific image being processed or reprogrammed for the different stages of the task. Previous work on FPGAs for computer vision has concentrated on the processing of intensity images. We present a technique that works on all three color bands (red, green, blue) of an image. 

    We are mapping an image clustering algorithm onto an FPGA-based computing platform that processes the input image and passes only the pixel classifications to the host PC. The result is a reduction of up to a factor of six of the number of bits of data required to process an image on a host PC. Further processing on the host PC includes region analysis and tag formation. The tags are then used for image analysis or searching for features in a digital library. This processing has many military applications such as finding people in databases or tanks in outdoor images.

PCD3: Richard B. Katz
NASA Goddard Space Flight Center

"Failure Modes of Programmable Technologies"

An overview of some of the failure modes of programmable technologies will be given. Specific examples will be given along with radiation results and laboratory analyses. Mitigation of faults and single point failure will also be discussed.

PCD5: Meenakshi Kaul, Vinoo Srinivasan, Sriram Govidarajan, Iyad Ouaiss and Ranga Vemuri
Digital Design Environments Lab (DDEL)

"Partitioning and Synthesis for Run-Time Reconfigurable Computers Using the SPARCS System"

    Modern FPGA's have the potential of being dynamically reconfigured. To take advantage of the `virtually' infinite resources on the FPGA boards, a design environment for FPGAs must have the capability to perform temporal and spatial partitioning integrated with synthesis.  SPARCS (Synthesis and Partitioning for Adaptive Reconfigurable Computers) is a vertically integrated collection of university and commercial tools for this purpose. SPARCS accepts behavior, RTL or gate level specificaitons in VHDL and, following temporal and spatial partitioning and behavioral/RTL/gate level synthesis and physical design, generates multiple bit-map file streams along with a reconfiguration schedule to dynamically reconfigure the target architecture. A variety of commercial target RC architectures are supported. SPARCS represents a significant advancement in the integration of highly efficient partitioning and synthesis algorithms for RC architecturesModern FPGA's have the potential of being dynamically reconfigured. To take advantage of the `virtually' infinite resources on the FPGA boards, a design environment for FPGAs must have the capability to perform temporal and spatial partitioning integrated with synthesis.

    SPARCS (Synthesis and Partitioning for Adaptive Reconfigurable Computers) is a vertically integrated collection of university and commercial tools for this purpose. SPARCS accepts behavior, RTL or gate level specificaitons in VHDL and, following temporal and spatial partitioning and behavioral/RTL/gate level synthesis and physical design, generates multiple bit-map file streams along with a reconfiguration schedule to dynamically reconfigure the target architecture. A variety of commercial target RC architectures are supported. SPARCS represents a significant advancement in the integration of highly efficient partitioning and synthesis algorithms for RC architectures.

    This paper describes the user's view of the SPARCS system and presents a case study of an image compression algorithm mapped from VHDL to the Wildforce reconfigurable computer using the SPARCS system.

PAB7: Kamal Khan
Actel Corporation

"Introducing Actel’s SX---Advantages of Programmable Interconnect Element & Sea of Modules in High Reliability Environment"

Actel has introduced its new Antifuse architecture in the form of SX family FPGAs. This family is based on the newest Actel’s architecture that utilizes Sea-of-Modules architecture and Programmable Interconnect Element. Clusters and SuperClusters form the basis of this Sea-of-Module Architecture with FastConnect and DirectConnect serving as local routing resources resulting in very high speeds--reaching over 250 MHz internal performance. This paper draws a comparison of SX devices to previous Actel devices--comparing architecture, performance, size, synthesis issues and in general system impacts. The SX architecture is compared to various synthesis styles and again a comparison is drawn to previous Actel devices.

PCD4: Scott Kniffin and Kusum Sahu
Unisys Federal Systems

"A Compendium of Total Dose Data on EEPROMs for NASA Programs"

This paper presents a summary of the variability in the TID radiation tolerance of SEEQ 32kX8 EEPROMs with lot date codes (LDC) varying from 9052 to 9530. These EEPROMs were evaluated for various NASA programs using low dose rate exposures varying from 0.01 to 0.08Rads(Si)/sec, from a 60Co source. The radiation tolerance of these parts varied from 3-40kRads(Si) depending upon the LDC. It was also found that the WRITE mode capability was generally lost at lower TID level than the READ mode capability. With increasing radiation exposures, some increase was also observed in power dissipation. The paper also presents the results of TID evaluations of 1Mbit EEPROMs from Hitachi and AMD.

C2: Rocky Koga
Aerospace Corp.

"SEFI IN EEPROM"

We have found Single Event Functional Interrupts (SEFIs) in EEPROMs (electrically erasable programmable read only memories). Since this class of device is read more often than written in most applications, we have attempted to measure the SEE sensitivities during the read process. During the read process, an EEPROM functions very similarly to a RAM. While reading, we have found incidences in which the control logic of the device appears to upset, in addition to the usual bit errors in the output. When this takes place, the normal EEPROM function ceases, yielding an unusual data output pattern. At this point we normally declare that we have observed a SEFI. Two different types of functional interrupt were observed.

B2: David Lamb and G. Kirchner
Theseus Logic and Honeywell Solid State Electronics Center

"Self -Timed Circuits for Adaptive Signal Processing Systems"

The evolution of silicon technology towards deep submicron devices and systems-on-a-chip is focusing attention on clocks as expensive necessities in today’s products and the limiting factor in tomorrow’s products. NULL Convention Logic™ (NCL) is a symbolically complete logic which integrates data transformation and control into a single language and thus produces circuits and systems which are inherently clockless, data driven and effectively delay insensitive. The unique features of this technology will be demonstrated through NCL CMOS ASICs designed in programs such as the Cascade Processor - an asynchronous, generally concurrent and adaptive processing architecture; Clockless Logic - a broadband digital receiver front-end for radar applications; the reconfigurable cell for an NCL FPGA; and an SOI CMOS cell library.

PCD7: P. Layton, D. Strobel, H. Anthony, R. Boss, P. Hsu
Space Electronics Inc.

"TID and SEE data on Rad Tolerant FPGA’s"

Radiation test data is presented for families of radiation tolerant FPGA’s. Actel-based antifuse technology Total Ionizing Dose (TID) data is presented for several die lots. Single Event Effects (SEE) data on reprogrammable 50,000 gate Gatefield based devices is also presented. Since the Gatefield device is Susceptible to Single Event Latchup (SEL), data on evaluation of a latchup protection for this device will also be presented.

PAB5: Mark Voyton and Adrian Macias
NASA Goddard Space Flight Center

"Using FPGAs as a Low Cost Implementation of IP Cores and Other High Density Designs"

The demands for low-volume and low-cost flight systems in aerospace applications increase dependence on programmable technology. The trend towards using Commercial-Off-The-Shelf (COTS) technology including Intellectual Property (IP) Cores and standards such as the Peripheral Component Interconnect (PCI) bus have further accelerated the use of programmable devices. NASA’s Small Explorer (SMEX) Lite Project has developed a flight system which, via programmable devices, implements low-cost IP Cores, and single-chip design solutions. This paper addresses the use of programmable devices to implement the PCI bus standard and the use of software tools for design including Hardware Description Language (HDL) synthesis, timing analysis, and simulation.        

B8: David Mavis, Mission Research Corporation, Bill Cox, FPGA Technologies, Dennis Adams, Northrop Grumman Corporation, and Richard Green, Aerospace Design Concepts (submitted by Terri Allahdadi)

Mission Research Corporation

"A Reconfigurable, Nonvolatile, Radiation Hardened Field Programmable Gate Array (FPGA) For Space Applications"

A new FPGA has been designed specifically for total dose tolerance and SEU immunity in space environments. The device uses CMOS/SONOS circuits for nonvolatile, reconfigurable programmation. A new tierable and nestable directional routing architecture enables the use of good rad-hard circuit design practices and specifically avoids the use of pass gates. The FPGA contains ~4k equivalent gates, is hardened to >200krad(Si) total dose, uses SEU immune programmation storage and SEU immune logic latches, and has control lines hardened to an LET > 100 MeV-cm2/mg for transient glitches. The architecture, software tools, and hardening techniques will be discussed.

B7: Jack McCabe
NASA Goddard Space Flight Center

    NASA’s Goddard Space Flight Center (GSFC), has accepted the broad range mission to expand and enhance research and development in the areas of Earth science, technology, and Space science. To achieve these goals GSFC must commit itself to excellence in scientific investigation, the development and operation of space systems and last but not least in the advancement of essential technologies. GSFC, during the past year, has developed a multi-faceted approach to address these long-term goals. One such approach is to apply recent commercial advances in field Programmable Gate Array (FPGA) technology to the new area of On-Orbit reconfigurable array based data processing.

    Reconfigurable processing is itself not new to the commercial world, but its successful application in Satellite instrument/data systems requires detailed attention not only to the standard environmental issues but more importantly to the effects of radiation. A satellite Instrument/data system, to operate as intended, must be fault tolerant to the radiation environment of earth’s orbit. This level of radiation tolerance can be achieved in many ways; the most robust and efficient method is to harden the silicon of those devices in the critical path of the functioning system. In an instrument/data system that implements reconfigurable array based processing the critical device that must be hardened to the effects of radiation is the reconfigurable FPGA (rFPGA).

    GSFC, in standing by its commitment to advance essential technologies, has embarked on a program that will over the next two years design, develop, test and fabricate radiation hardened reconfigurable Field Programmable Gate Array (RH rFPGA) devices. GSFC is partnered with Sandia National Laboratories, Honeywell and Atmel to bring about the successful conversion of the commercial AT6010 to the RH rFPGA device. The RH rFPGA device will pave the way for the development of Rad-Hard reconfigurable array based information systems for space flight applications in the areas of display, analysis, archiving and distribution
of space and Earth science data.

PAB3: Paul McGaugh and Kamal Khan
Southwest Institute and Actel Corporation

"VHDL Synthesis for Space Applications--Implementing VME Core in Actel RadHard Devices Using Actmap"

    One of the main concerns in space applications is the ability of the programmable logic device to withstand a high radiation dose with improved Single Event Upset (SEU) and elimination of proton-SEU sensitivity. Field Programmable Gate Array (FPGA) designs using High-level Design Language (HDL) like VHDL requires that these concerns be given utmost importance while developing the code. The code has to be written according to the environment conditions available to the application. One may have to implement Triple Modular Redundancy (TMR), a well-known technique for SEU mitigation, in their code or they may have to avoid using the SFF portion of the S-module.

    This paper presents a short analysis of implementing a VME Core in VHDL using Actmap- Actel’s VHDL Synthesis tool. Various techniques are implemented and studied according to their radiation-harness ability. The VMEbus has applications in the electronic world as a global parallel interconnect supporting 8- 64 bit processors and datapaths. Data transfers are based on a non-multiplexed asynchronous protocol, which allows transfers between bus masters and slaves (e.g. processor and memory card) to be performed at the highest speed that the slowest card will allow. Our application is the implementation of the VME Core used on various boards including Command Telemetry Module and Instrument Interface Module (IIM) using Actel Corporation RH1280 FPGA. These devices offer a total dose radiation-harness in excess of 300K rads (Si) with guaranteed latch-up immunity.

C3: P.J. McNulty¹, L.Z. Scheick¹, and D.R. Roth^2
1Dept. of Physics and Astronomy, Clemson University, Clemson, SC 29634-1911
²Applied Physics Laboratory, Johns Hopkins University, Laurel, MD, 20723-6099

"Monitoring the Natural Radiation Environments in Space Using UVPROM Technology"

Two methods are described for measuring ionizing radiation on spacecraft. The first method measures the charge remaining on the floating gates of an array of FAMOS transistors in a UVPROM by reading the device while varying the programming voltage. This method is suitable for measuring the average absorbed dose on MOS devices flown on satellites. Reading the detector leaves the data and the detector intact and capable of continued measurements of the accumulated dose. Results from an experiment using this technique aboard the MPTB satellite are discussed. The second method uses UV radiation and is capable of measuring the absorbed dose on each of the 64K memory elements. The data generated by this procedure should be suitable to benchmark models that predict the distribution of absorbed dose across the die. Such models facilitate the prediction of the onset of the first-bit failure. First-bit failure is, in most cases, the catastrophic impact of total dose exposure on MOS devices.

B4: Anil Reddy
Chip Express Corporation

"LPGA Technology for Military & Aerospace ASIC Applications"

Chip Express' unique LPGA (Laser Programmable Gate Array) technology offers a variety of ASIC products providing 883-B MIL STD Military Reliability Screening. With the unique capability to process one wafer at a time using only OneMask Chip Express is efficiently addressing the military market low volume requirements. In addition, the LPGA has passed various RAD-HARD tests conducted by NASA. The test results indicate that LPGAs are suitable for a range of space flight mission applications. Chip Express allows military design conversions from obsolete ASIC to more advanced process technologies. This paper discusses the LPGA technology, tools and methodology, device architecture, performance and process flow and options for Mil Std. 883 style screening.

PAB4: Daniel E. Rodriguez
The Johns Hopkins University/Applied Physics Laboratory

"A Simplified PCI Backplane Approach for the TIMED Spacecraft Integrated Electronics Module"

    The NASA Thermosphere-Ionosphere-Mesosphere Energetics and Dynamics (TIMED) Spacecraft employs an Integrated Electronics Module (IEM) containing digital and RF subsystems for command and data handling, uplink and downlink signal processing, GPS navigation, and power conditioning. The fundamental design requirement for the communication path between several of these subsystems calls for a multi-master bus with a data transfer capability of 5 Mbytes/sec. Further requirements impose implementation of a bus controller within a single gate array device and utilization of commercially available test equipment for stand-alone board level testing. This article describes how the system requirements were satisfied by the selective implementation of the PCI bus specification. The design consists of a master and target controller co-existing within a single Actel, A1280A field-programmable gate array. Restricting the layout to combinational logic modules yields an SEU resistant design capable of withstanding the mission radiation environment.

PAB2: Mike Sandor and Shri Agarwal
JPL

"A Step Towards Infusion of Reliable COTS Plastic Parts into NASA Flight Hardware"

Several critical issues related to the use of COTS parts were identified which included PEMs moisture sensitivity, upgrading to military temperature range, radiation sensitivities, risk methodologies, supplier selections, and total cost of ownership of COTS that must meet minimum mission requirements. These issues were reviewed and evaluated for their applicability to NASA environments. Based on the results obtained a preliminary flow was developed for infusion of reliable COTS parts into NASA flight hardware. This flow is being used for a time critical flight project. In addition, a demonstration of recently launched COTS website will be given.

D5: Jason Scott, Sandeep Neema, Ted Bapty, Janos Sztipanovits
Vanderbilt University

"Model-Integrated Environment for Adaptive Computing"

    Many high-performance, embedded applications must function in rapidlty changing environments. Power/size constraints limit hardware size, while performance requirements demand algorithm-specific architectures. Reconfigurable computing devices allow the architecture to change in response to the changing environment.

A model-integrated approach is used for the synthesis of these systems. The target systems are built on a heterogeneous computing platform: including configurable hardware, ASIC and general purpose processors and DSPs. The model interpretation process will generate hardware/software architecture specifications and a run-time Configuration Manger allowing dynamic adaptation to changing environments while the synthesized system is on-line. The synthesis process will optimize hardware/software architectures for user-definable cost functions such as weight, power, algorithmic accuracy and flexibility.

    An example application has been modeled and synthesized using FPGAs and DSPs for processing elements that implements a component of an missile elevation/azimuth controller.

"Reprogrammable, Non-Volatile EEPROM Multi-Chip Module (MCM) for Radiation-Hardened Space Applications"

PAB1: Michael Stebnisky
Lockheed Martin

TBA

    CYPRIS (Cryptographic RISC microprocessor) is a high performance, algorithm agile reconfigurable processor specifically designed to address the cryptographic requirements of military software radios and wireless systems. Designed under a NSA contract, CYPRIS was optimized to implement a variety of legacy COMSEC and TRANSEC algorithms while enabling field upgrades to new and emerging INFOSEC algorithms. CYPRIS contains a high performance RISC core, a reconfigurable hardware unit, and a suite of programmable and automatic system check features. Unprogrammed, CYPRIS is an unclassified, non CCI, exportable device; when programmed it assumes the classification of its software. Over 20 core cryptoalgorithms have been developed.

PCD2: Adrian Stoica, Carlos-Salazar Lazaro, Raoul Tawel
JPL

"Evolvable Electronic Systems"

Increasingly more flexible reconfigurable devices bring closer the perspective of dynamically reconfigurable, adaptive information processing. An automated self-reconfiguration of these devices would be very useful. Evolvable Hardware is a new research area in which search algorithms, in particular evolutionary algorithms, are applied to automatically determine/ synthesize/reconfigure programmable devices. In this paper we review current work in evolving analog circuits and present our results on simulated evolution of analog circuits on programmable transistor arrays.

C4: Gary Swift
Jet Propulsion Laboratory / California Institute of Technology

The Use of Advanced Flash Memories in Satellite Applications: Radiation Responses and Mitigation Choices

The density (16 to 128Mbits) and non-volatility of modern, single-voltage flash memories make them particularly attractive to designers for space applications due to resulting savings in mass, volume, and power.  The variety of manufacturers producing commercial flash devices makes it likely that of at least one can be found having suitable (fortuitous) radiation resistance. This presentation summarizes test results obtained part way through an ambitious survey of single-event and total-dose responses of current flash choices. Additionally, a number of trends can be identified, including internal architectural considerations affecting total dose responses and operational choices that reduce the occurrence and effects of complex upset modes.

D4: Jeffrey Walrath and Ranga Vemuri
University of Cincinnati

"A Performance Analysis Environment for Adaptive Computing Systems"

    ARC (Analyzer for Reconfigurable Computers) is a comprehensive performance modeling and analysis environment for adaptive and reconfigurable architectures. ARC contains an advanced performance modeling language named PDL+ which provides numerous high-level constructs for the specification of reconfigurable devices and hierarchical composition of these devices into reconfigurable systems. ARC is a comprehensive tool facilitating modeling of numerous attributes including throughput rate, clock speed, power consumption, reliability and so forth, at arbitrary levels of abstraction including the hardware level or any of the adaptive software layers in the system.

    Our paper presents a detailed user's view of the ARC system and explains how to model and analyze a variety of reconfigurable devices and systems at both hardware and software levels of abstraction. Modeling of a variety of performance and non-functional attributes will be illustrated through examples as well. We will also explain how ACS designers, ACS software (compilers, synthesis tools) developers and ACS application developers can benefit from the capabilities of ARC and by utilizing its interactive shell/GUI and its API (application procedure interface).

C1: J. J. Wang, B. Cronquist, J. McCollum, Actel Corp. D. Patel, and R. Katz,
Actel Corp, Lockheed-Martin Federal Systems, and NASA/Goddard Space Flight Center

"Development of Total Dose Hardened Antifuse FPGA"

    The product development of a total dose hardened, QML antifuse field programmable gate array (FPGA) is presented. A commercial design, A1020B, is processed by a hardened process to meet most space radiation total dose requirements. Significant modification of the device, process and circuit design was done to optimize the wafer yield, programmability, and single event effects (SEEs). Key product differences between the commercial and rad-hard version are compared. Extensive single event upset (SEU) tests were performed to study the sensitivity of the clock circuit. Special DUT (device under test) design to count the upset rates due to clock circuit was implemented. SEU rates simulation were also done for a typical geostationary orbit to evaluate the upsets due to the clock circuit.

PCD12: Darren Wesemann
Xanthon, Inc.

"Virtual Processing: Simplified Application Development Across a Community of Resources"

    Xanthon's Virtual Processing* environment combines an innovative software framework, high-performance adaptive hardware platform, application libraries and an application development methodology.  Virtual Processing Technology involves an implementation methodology and an abstract resource management system called ViPrNET*.   The main goal of ViPrNET is to reflect the nature of real-world applications in an enhanced framework, by providing an application model that simplifies the definition of a process, and then manages the complexities of distributed execution to all processing resources of the system.

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