(MAPLD Conference)
PCD5: Meenakshi
Kaul, Vinoo Srinivasan, Sriram Govidarajan, Iyad Ouaiss and Ranga Vemuri
Digital Design Environments Lab (DDEL)
"Partitioning and Synthesis for Run-Time Reconfigurable Computers Using the SPARCS System"
Modern FPGA's have the
potential of being dynamically reconfigured. To take advantage of the `virtually' infinite
resources on the FPGA boards, a design environment for FPGAs must have the capability to
perform temporal and spatial partitioning integrated with synthesis. SPARCS
(Synthesis and Partitioning for Adaptive Reconfigurable Computers) is a vertically
integrated collection of university and commercial tools for this purpose. SPARCS accepts
behavior, RTL or gate level specificaitons in VHDL and, following temporal and spatial
partitioning and behavioral/RTL/gate level synthesis and physical design, generates
multiple bit-map file streams along with a reconfiguration schedule to dynamically
reconfigure the target architecture. A variety of commercial target RC architectures are
supported. SPARCS represents a significant advancement in the integration of highly
efficient partitioning and synthesis algorithms for RC architecturesModern FPGA's have the
potential of being dynamically reconfigured. To take advantage of the `virtually' infinite
resources on the FPGA boards, a design environment for FPGAs must have the capability to
perform temporal and spatial partitioning integrated with synthesis.
SPARCS (Synthesis and Partitioning for Adaptive Reconfigurable
Computers) is a vertically integrated collection of university and commercial tools for
this purpose. SPARCS accepts behavior, RTL or gate level specificaitons in VHDL and,
following temporal and spatial partitioning and behavioral/RTL/gate level synthesis and
physical design, generates multiple bit-map file streams along with a reconfiguration
schedule to dynamically reconfigure the target architecture. A variety of commercial
target RC architectures are supported. SPARCS represents a significant advancement in the
integration of highly efficient partitioning and synthesis algorithms for RC
architectures.
This paper describes the user's view of the SPARCS system and presents
a case study of an image compression algorithm mapped from VHDL to the Wildforce
reconfigurable computer using the SPARCS system.
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