(MAPLD Conference)
PAB9: Miriam Leeser
Northeastern University, Dept. of Electrical and Computer Eng.
"Color and Spatial Clustering for Image Analysis with an FPGA-based Computing System"
FPGA platforms are ideally suited for the initial processing of images for computer vision. The large amount of image data can be preprocessed by exploiting the inherent parallelism available in FPGA architectures and effectively keeping unnecessary amounts of data off the host processor. FPGA implementations can be specialized to the specific image being processed or reprogrammed for the different stages of the task. Previous work on FPGAs for computer vision has concentrated on the processing of intensity images. We present a technique that works on all three color bands (red, green, blue) of an image.
We are mapping an image clustering algorithm onto an FPGA-based computing platform that processes the input image and passes only the pixel classifications to the host PC. The result is a reduction of up to a factor of six of the number of bits of data required to process an image on a host PC. Further processing on the host PC includes region analysis and tag formation. The tags are then used for image analysis or searching for features in a digital library. This processing has many military applications such as finding people in databases or tanks in outdoor images.
Our algorithm compresses a true color digital image represented as red green and blue components using spatial clustering. The resulting image pixels are represented by their class, which can result in a reduction in the size of the original image by a factor of six. By using clustering, the classess represent the image without loss of important features. The tags are calculated on the basis of current image color content. Therefore, this method is applicable to different types of scenes (indoor vs. outdoor) as well as different weather or lighting conditions.
We are mapping the algorithm onto an Annapolis Microsystems Wildforce board (the commercialization of the Splash-2 architecture) with four Xilinx 4028s. Each has 500MB local memory, and is used to classify a 240x256 sized image. The pixel classes are then passed on to a PC for tag formation and image analysis.
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