(MAPLD Conference)
PAB5: Mark Voyton and Adrian Macias
NASA Goddard Space Flight Center
"Using FPGAs as a Low Cost Implementation of IP Cores and Other High Density Designs"
The demands for low-volume and low-cost flight systems in aerospace applications increase dependence on programmable technology. The trend towards using Commercial-Off-The-Shelf (COTS) technology including Intellectual Property (IP) Cores and standards such as the Peripheral Component Interconnect (PCI) bus have further accelerated the use of programmable devices. NASA’s Small Explorer (SMEX) Lite Project has developed a flight system which, via programmable devices, implements low-cost IP Cores, and single-chip design solutions. This paper addresses the use of programmable devices to implement the PCI bus standard and the use of software tools for design including Hardware Description Language (HDL) synthesis, timing analysis, and simulation.
Home
Last Revised: July 03, 2002
Digital Engineering Institute
Web Grunt: Richard Katz
