(MAPLD Conference)
D4: Jeffrey Walrath
and Ranga Vemuri
University of Cincinnati
ARC (Analyzer for Reconfigurable Computers) is a comprehensive performance modeling and analysis environment for adaptive and reconfigurable architectures. ARC contains an advanced performance modeling language named PDL+ which provides numerous high-level constructs for the specification of reconfigurable devices and hierarchical composition of these devices into reconfigurable systems. ARC is a comprehensive tool facilitating modeling of numerous attributes including throughput rate, clock speed, power consumption, reliability and so forth, at arbitrary levels of abstraction including the hardware level or any of the adaptive software layers in the system.
Our paper presents a detailed user's view of the ARC system and explains how to model and analyze a variety of reconfigurable devices and systems at both hardware and software levels of abstraction. Modeling of a variety of performance and non-functional attributes will be illustrated through examples as well. We will also explain how ACS designers, ACS software (compilers, synthesis tools) developers and ACS application developers can benefit from the capabilities of ARC and by utilizing its interactive shell/GUI and its API (application procedure interface).
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