(MAPLD Conference)
B2: David Lamb and
G. Kirchner
Theseus Logic and Honeywell Solid State Electronics Center
"Self -Timed Circuits for Adaptive Signal Processing Systems"
The evolution of silicon technology towards deep submicron devices and systems-on-a-chip is focusing attention on clocks as expensive necessities in today’s products and the limiting factor in tomorrow’s products. NULL Convention Logic™ (NCL) is a symbolically complete logic which integrates data transformation and control into a single language and thus produces circuits and systems which are inherently clockless, data driven and effectively delay insensitive. The unique features of this technology will be demonstrated through NCL CMOS ASICs designed in programs such as the Cascade Processor - an asynchronous, generally concurrent and adaptive processing architecture; Clockless Logic - a broadband digital receiver front-end for radar applications; the reconfigurable cell for an NCL FPGA; and an SOI CMOS cell library.
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