(MAPLD Conference)
B0: John Birkner
VP, Co-founder, QuickLogic Corp
"From Simple PALs to High-Speed, High-Density Leading Edge FPGA's, Their Technologies
and Applications"
Born in the decade of 1970’s to reduce 54/74 TTL logic chip count, programmables empowered design engineers with a "design your own chip" methodology. Using standard, off-the-shelf product, the engineers’ PAL enabled multiple-spin, design exploration, squeezing maximum functionality into single PCBs, exemplified in design-wins such as the Apple Macintosh and Ms. PACMAN. The vision of early PLDs was to use memory technology to implement logic, allowing concise Boolean equations to customize glue-logic functions, compared to net-lists of gates strung out over multiple schematic pages. When this PLA, sum-of-product-term array pushed the limits of power and density, FPGAs emerged to increase flexibility/density and decrease power by employing extravagant use of true, 2-terminal switch technology, interconnecting seas of logic cells in gate-array fashion. As gates now become “free”, programmables are tuning-up IP core and embedded standard product IP core functions for ready-to-use bus-interface, processor and DSP applications. Will programmables succeed in winning their ultimate challenge . . . the race to system-on-chip?
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Last Revised: February 03, 2010
Digital Engineering Institute
Web Grunt: Richard Katz
