(MAPLD Conference)
A3: Grason Curtis
Synplicity
"Embedded Synthesis: A New Design Methodology for Deep-Submicron Programmable Logic Devices"
In the past three years, the programmable logic industry has experienced a dramatic shift in both density and complexity. As densities increased, new design methodologies were required. Schematic and equation based design entry worked for simple PLD’s and even low-density FPGA’s. But as PLD’s pushed above 10K gates, Hardware Description Languages (VHDL and Verilog) became necessary to satisfy decreasing design schedules. Synplicity introduced Synplify in 1994 as the first synthesis tool written from the ground up specifically for programmable logic optimization. As CPLD and FPGA’s continue to migrate down into deep-submicron geometry’s, a new design methodology again will be required. Issues prevalent in ASIC design: physical placement, routing delays, advanced timing optimization, intellectual property cores, etc. are now starting to be seen in the high density FPGA/CPLD design. To meet these new challenges, Synplicity introduced a new methodology called Embedded Synthesis: the linking of logic synthesis and physical design. This presentation will describe Embedded Synthesis and its impact on deep-submicron programmable logic design.
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