(MAPLD Conference)
A1: Joe Bogdanski
APL
"Space Qualified Large Memory Array Implementation for a Solid State Recorder"
This talk chronicles the design of a solid state recorder (SSR). The SSR’s design was developed for the Goddard supported Command and Data Handling In your Palm project. The design was later modified and used for the TIMED satellite. Commercial parts, principally DRAM and FPGAs which are susceptible to single event upset (SEU) from protons or heavy ion particles, dramatically influenced the SSR’s design. Techniques for detecting and correcting SEUs in sensitive parts were extensively used, these included block error codes on data and voting hardware logic.
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Last Revised: July 03, 2002
Digital Engineering Institute
Web Grunt: Richard Katz
