Ronald Reagan Building and International Trade Center
Washington, D.C.
September 9-11, 2003
Seminars
Allan Snavely
Dr. Snavely is an expert in high performance computing. He has contributed to the development of a number of strategies for working around the Von Neumann bottleneck to deliver fast time-to-solution for scientific applications. These include fundamental studies in modeling to understand the factors that effect performance; also architectural innovations including multithreaded computing, and computing with field-programmable gate arrays (FPGAs). Snavely’s current research involves the design and optimization of complex systems (including supercomputers and computing Grids) drawing on principles of economics and statistics and leveraging reconfigurability.
Snavely is leader of the Performance Modeling and Characterization Laboratory (PMaC) at the San Diego Supercomputing Center (SDSC), charged with understanding and addressing factors that affect performance on large supercomputers and Grids. Current grants include work on developing accurate performance models for applications on HPC systems and one to form the Performance Evaluation Research Center (PERC), involving DoE labs universities, and is the Principal Investigator in charge of modeling and analysis. Snavely is a founding member of the Grid Benchmarking Research Group in the Global Grid Forum with a charge to develop meaningful metrics for Grid performance. He is on the HPC Users Forum Steering committee and he works with the Forum to collect and publish high performance computing data, and to develop ways of meaningfully comparing machines for capability.
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