Ronald Reagan Building and International Trade Center
Washington, D.C.
September 9-11, 2003
Seminars
2002 MAPLD International Conference Seminars
The 2003 MAPLD International Conference is offering seminars on Monday, September 8, 2003. You may sign up for a seminar when registering for the conference.
The 2003 MAPLD seminars will run in two parallel tracks, each for six hours. The seminars will include both hardcopy notes and a CD-ROM with all material.
Seminars for the 2003 MAPLD International Conference:
Advanced Design: Digital Signal Processing, Programmable Device Architecture, and Military/Aerospace Applications. (6 hours, full day). Starts 9:30 am in Meridian C with breaks at 11:00 am and 3:45 pm.
Seminar Leader: Ray Andraka, The Andraka Consulting GroupAbstract
Digital signal processing has traditionally been done using Von-Neuman or Harvard type processors with enhancements such as single cycle multiplies. Recent advances in speed, density, and features have made Field Programmable Gate Arrays (FPGAs) very attractive for digital signal processing applications, particularly when performance requirements are beyond the capability of microprocessors. Unfortunately, the majority of signal processing work over the last quarter century has been implemented as software on computers. Consequently, there is currently very little overlap between hardware design and DSP expertise. Algorithms developed for software platforms are usually very inefficient for direct hardware implementation, and without the overlapping areas of expertise, the resulting FPGA realization is bound to disappoint.
This seminar helps to bridge the gap between DSP and FPGA design, aiding the designer in achieving the performance potential of FPGAs. This seminar will first review computer arithmetic and then look in detail at efficient FPGA implementations of common DSP elements such as multipliers, filters, and mixers. Tradeoffs between clock rate and performance will be discussed along with several design examples.
Reconfigurable Computing: FPGA-Based, General Purpose, High Performance Systems. (6 hours, full day). Starts 9:30 am in Meridian E with breaks at 11:00 am and 3:45 pm.
Seminar Leaders:Abstract (Extended Abstract)
The synergistic advances in high-performance computing systems and in reconfigurable computing, based on field programmable gate arrays (FPGAs), form the basis for a new paradigm shift in high-performance computing, namely reconfigurable supercomputing. This can be achieved through hybrid systems of microprocessors as well as FPGA modules that can leverage the system level concepts from high-performance computing and extend them to accommodate reconfigurations. Such systems inherently support both fine-grain and coarse-grain parallelism, and can dynamically tune their architecture to fit the applications. Many researchers have recognized this and advances are proceeding at three system levels. At the networked computing level, researchers have extended job management systems to recognize networked reconfigurable resources and exploit their power, in a grid computing fashion. Progress has been also made in programming and managing computer clusters, with reconfigurable co-processors. Finally, steps have been taken towards the development of massively parallel systems of conventional microprocessors and reconfigurable computing capabilities. Programming such systems can be quite challenging as programming FPGA devices can essentially involve hardware design. To address this, there have been very significant developments in compiler technologies and programming tools for some of these systems. This tutorial will introduce the field of reconfigurable supercomputing and advances made in systems, programming tools, applications, and compiler technology.
Thanks,
We hope to see you at MAPLD 2003,
Richard B. Katz
National Aeronautics and Space Administration
mapld2003@klabs.org
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