Tanya Vladimirova, David Eamey, Sven Keller, Martin Sweeting
Surrey Space Centre, School of Electronics and Physical Sciences
University of Surrey
Summary
Previously, work has been reported on the design of a single-chip on-board computer (SoC-OBC) for a small satellite [1,2,3]. This paper focuses on a particular peripheral core for the SoC-OBC – a 32-bit floating-point co-processor capable of computing 17 mathematical functions – addition, subtraction, multiplication, division, sine, cosine, tangent, inverse sine, inverse cosine, inverse tangent, hyperbolic sine, hyperbolic cosine, hyperbolic tangent, inverse hyperbolic tangent, exponential function, square root and natural logarithm. The co-processor is based on the Co-ordinate Rotation Digital Computer (CORDIC) algorithm and conforms to the IEEE-754 standard for single-precision (32-bit) floating-point numbers, handling overflow, underflow and special number representations, such as infinity and not-a-number [4].
An RTL specification of the co-processor was captured in VHDL, however before any VHDL work was carried out, the floating-point operation of the CORDIC algorithm was fully investigated via software modelling at bit-level using the C programming language. Comprehensive investigation of the accuracy and correctness of the numerical results, generated by the co-processor, was undertaken, which has shown that, overall, the accuracy of the co-processor is extremely good [4]. The RTL design was fully tested and debugged, leading to the final version of the VHDL code, which was then synthesised and implemented on a high-density FPGA (XILINX Virtex XCV800). The co-processor was integrated with the LEON SPARC V8 microprocessor core and its operation was tested on a XILINX Virtex XCV800 FPGA. The co-processor showed good performance speeding up the execution of the Whetstone benchmark by 60%.
The paper will outline the co-processor design and will discuss its integration with the LEON microprocessor core. Results, illustrating the performance of the co-processor, will be presented.
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D.Zheng, T.Vladimirova, M.Sweeting. "A CCSDS-Based Communication System for a Single Chip On-Board Computer", Proceedings of the 5th Military and Aerospace Applications of Programmable Devices and Technologies International Conference (MAPLD'2002), D5, September 2002, Laurel, Maryland, US.
D.Zheng, T.Vladimirova, H.Tiggeler. M. Sweeting. Reconfigurable Single-Chip On-Board Computer for a Small Satellite - 52nd International Astronautical Congress, Toulouse, France - October 1-5, 2001, IAF-01-U3.09.
T.Vladimirova, D.Eamey. 32-Bit Floating-Point Mathematical CORDIC Co-Processor – submitted to the 13th International Conference on Field Programmable Logic and Applications FPL03, September 1-3, 2003.