Jim Lewis
SynthWorks Design Inc.Introduction
This paper will summarize VHDL enhancements being made by several IEEE working groups. You will note that the plural "groups" is correct as VHDL designers actually use several standards. A few of these are IEEE 1076 (the language), IEEE 1164 (the package std_logic_1164), IEEE 1076.3 (the package numeric_std plus the proposed packages for floating point), and IEEE 1076.6 (VHDL RTL Synthesis). In 2003 all of these groups have been actively updating their part of the language.
Abstract
With all the media hype about languages such as Verilog/SystemVerilog, Vera, and specman e where does the future of VHDL lie? 2003 has heard many claims about VHDL being "The New Latin" and it is dead. Fortunately these claims were made by people or companies who have very little interest (or market share) in VHDL and are looking to push the market in their direction.
February of 2003 saw the kick off of VHDL-200X. VHDL-200X's charter is to enhance VHDL to improve performance, modeling capability, ease of use, verification features, simulation control, and the type system. This looks like the big revision that we (designer and verification engineers) have been looking for.
Going beyond the base language effort, enhancements are being added to the packages std_logic_1164 and numeric_std are being added. The changes to the existing packages is evolutionary. The revolutionary news is the proposed addition of a package to support synthesis of floating point types.
The standard IEEE 1076.6 (VHDL 1076.6) should be in the IEEE ballot process by the time of MAPLD-03. If a designer writes a model that is compliant to this standard, it will synthesize on all compliant synthesis tools. The current version of this standard, 1076.6-1999, kept the coding styles simple so it was easy for most EDA vendors to achieve compliance. The new draft enhances this significantly by both adding to the set of RTL objects that can be synthesized (such as RAMs) and increasing the flexability and ease of use of some of the modeling styles.
Why are we bothering to update VHDL when popular market share statistics say that Verilog has 70% of the US market? An important note about these statistics is that they are based solely on market share. Market share is based on dollars spent yearly on EDA tools. Hence the ASIC market, who must buy expensive tools, eliminates the FPGA market from consideration. The statement that I have heard again and again is that most FPGA designs are done with VHDL. I have even heard rumors at one point in time that Verilog was not even second in the FPGA design market.
With the new features of VHDL-200X, VHDL will transition from being a simple HDL (hardware to description language) to a HDVL (hardware design and verification language). This will be a huge benefit for the users. Not only will we benefit from improved ease of use, but with the new features, there will no longer be any argument to learn an additional language such as Vera, SystemC, or specman e to help with verification.
References
The following websites have information about the various groups doing work on the VHDL standards.
- IEEE 1076/VHDL-200X: http://www.eda.org/vhdl-200x
- IEEE 1164: http://www.eda.org/vhdl-std-logic
- IEEE 1076.3/numeric std: http://www.eda.org/vhdlsynth
- IEEE 1076.3/floating point: http://www.eda.org/fphdl
- IEEE 1076.6: http://www.eda.org/siwg