SEU Mitigation Techniques for Low-Power, High Speed Microprocessor

David Czajkowski
Space Micro

Abstract

Research was completed on an ultra-low power space computer architecture, which highly leverages commercial microprocessor technology, combining several low power techniques currently used for PDAs and laptop computers. The research included development of a unique patent-pending SEU mitigation technique, called Time-Triple Modular Redundancy, which enables detection and correction of SEUs in a microprocessor. A simulation of the mitigation technique was completed to determine the feasibility on a Very Long Instruction Word microprocessor. From other research, the new mitigation technique’s performance was estimated. The benefits of using this technology in a satellite computer are also estimated.