Rajan Bedi
Astrium-SpaceSummary
Future low-cost, deep-space missions and Earth-orbiting satellites will be made possible through the use of advanced, highly-integrated, miniaturised, autonomous microsystems. Such systems will be built around single chip solutions using commercial foundries with special design and process enhancements for radiation hardness and extreme conditions in space.
One possible architecture could comprise a complete system-on-chip (SOC) for spacecraft control based around a SpaceWire network encompassing the following functional blocks:
- On-board Baseband DSP
- Analog RF Transceiver
- Power Management
- On-board Storage
- System Control
- Guidance & Navigation
- Sensors
The benefits of an integrated SOC approach would be lower power consumption, smaller mass, higher reliability, greater levels of reusability and improved system testing and quality all of which contribute to the spirit of "Faster, Better, Cheaper".
An integrated SOC approach would also make the space microelectronics roadmap consistent with trends in the commercial semiconductor industry. The recent revolution in wireless communications has resulted in significant technological advances in the design and manufacture of single chip radio transceivers. The development of mixed-signal integrated circuits has produced mobile devices that have delivered the above benefits.
In terms of on-board data processing for satellite communications, Astrium-Space has started to investigate the potential advantages of extending the boundaries of the payload DSP to include analog and mixed-signal circuitry.
We have started to develop mixed-signal simulation models to enable system-level analysis of the analog-digital interface for satellite DSP payloads, with the view to optimising this mixed-signal connection. The design of simulation models for the complete analog processing chain, including analog-to-digital conversion (ADC) and digital-to-analog conversion (DAC), will allow for experimentation of device parameters in the mixed-signal processing chain. The results of this analysis can be used:
- To influence the specification and sourcing of ADC devices that can be used with future DSP payloads.
- To prevent unnecessary under-design or over-specification.
- To establish the tolerance levels and to identify the limits to which circuit functionality and payload performance can be guaranteed in terms of ADC/DAC linearity, resolution, bandwidth etc.
- To understand how non-ideal ADC/DAC devices impact the overall system error budget and how this will affect the performance of a satellite payload.
To develop accurate and reliable behavioural models for mixed-signal processing, the ADC/DAC static error sources must be modeled correctly. These 'd.c.' sources are: Offset Error (OE), Gain Error (GE), Differential Nonlinearity (DNL) Error and Integral Nonlinearity (INL) Error.
The simulation models have been implemented using a mixed-signal hardware description language as part of a modern SOC design flow. This approach enables ADC/DAC and other mixed-signal intellectual property blocks to be connected directly to the DSP payload for analyses using EDA tools, e.g. high-level system verification, power consumption, speed, area and design-for-test.
Results
To date, an ADC model has been developed that allows control over the following parameters: resolution, full-scale voltage range, input amplitude, input frequency, sampling frequency, mid-rise/mid-thread quantisation and clock jitter. In addition, the user has full control over OE, GE, DNL and INL, which may be obtained directly from a manufacturer's datasheet. The ADC model predicts the effects of the above simulation parameters and static error constraints on typical a.c. performance metrics such as signal-to-noise ratio, spurious free dynamic range and noise power ratio testing.
The simulation environment has also been used to investigate how two lower specification ADCs can be used to emulate a single higher performance converter for possible use on a new broadband satellite. Two ADCs can be connected in parallel to double the effective sampling rate by clocking one 180* with respect to the other. Results from combined spectra show that the sampling rate can be increased but if the input amplitude is not backed-off sufficiently, the static error sources affect performance. The outputs from two ADCs connected in parallel but driven by the same sampling clock can be averaged to mitigate the random nonlinear DNL and INL effects. Results from combined spectra show an improvement in performance over that achieved by each individual ADC.
Future Work
The simulation environment is to be expanded to include a DAC and signal conditioning circuitry such as an amplifier to allow analysis of the complete mixed-signal processing chain including the DSP payload. This will enable important design decisions to be made as to how accurate each device in this chain must be and how these choices impact the overall system error budget and performance of the on-board DSP, i.e. how non-ideal ADCs/DACs affect the satellite payload. The ultimate aim is an integrated, single chip, mixed-signal DSP for space communications.
The simulation environment is also to be used as a platform to investigate the potential advantages of digitising the transceiver architecture for a regenerative telecommunications satellite payload.