NASA Office of Logic Design

A scientific study of the problems of digital engineering for space flight systems,
with a view to their practical solution.

2003 MAPLD International Conference

Ronald Reagan Building and International Trade Center
Washington, D.C.

September 9-11, 2003

Abstracts

Invited and Special Talks
(Talks sorted by Technical Session)

Paper A0
"Welcome and Opening Remarks"
Theron M. Bradley Jr.
Chief Engineer, NASA

Paper A6
"An Application Engineer's View"
Brendan Bridgford¹ and Dan Elftmann^2
1 Xilinx Corporation
²Actel Corporation
Abstract: apps_engineer.html

Paper D0
Invited History Talk: Roger D. Launius, Smithsonian Air and Space Museum
"After Columbia: How We Got into this Fix and How We Can Get Out of It"

Regular Papers (sorted by last name of the first author)

Paper P1
"Looking for Speed!! Go Optical: Ultra-Fast Photonic Logic Gates for the Future Optical Communication and Computing"
Hossin Abdeldayem¹, Donald O. Frazier², Benjamin Penn², and Mark S. Paley^2
1 NASA Goddard Space Flight Center
² NASA-Marshall Space Flight Center
Abstract: abdeldayem_a.pdf, abdeldayem_a.doc

Paper P2
"Porting EDIF netlists to the Viva Environment"
Sreesa Akella, Duncan A. Buell, and James P. Davis
Department of Computer Science and Engineering, University of South Carolina
Abstract: akella_a.pdf, akella_a.doc

Paper P3
"A Modeling and Exploration Framework for Mapping of Linear Array of Tasks onto Adaptive Computing Systems"
Egor Andreev, Sumit Mohanty, and Viktor K. Prasanna
University of Southern California
Abstract: andreev_a.pdf

Paper B3
"A Methodology for Optimized FPGA Design of Signal Processing Kernels"
Zachary K. Baker and Viktor K. Prasanna
University of Southern California
Abstract: baker_a.pdf

Paper C2
"SEU Tolerant Controls for a Space Application based on Dynamically Reconfigurable FPGA"
Stefano Baldacci, Francesco Cuzzocrea, Alessandro Donati, and Tommaso Ramacciotti
Kayser Italia Srl. Livorno Italy
Abstract: baldacci_a.html

Paper P100
"Managerial and Contractual Issues in a Mission-Critical Air Force Project"
Rod Barto
NASA Office of Logic Design
Abstract: barto_abstract_p100.doc

Paper P4
"In-System Debugging for Design Verification"
M. Beardslee
Synplicity, Inc.
Abstract: beardslee_a.pdf, beardslee_a.doc

Paper P5
"Mixed-Signal Processing for Space Communications"
Rajan Bedi
Astrium-Space
Abstract: bedi_a.html

Paper A7 (Wed)
"Secure HDTV Transport Over IP Networks"
Peter Bellows, Jaroslav Flidr, Ladan Gharai, and Colin Perkins
USC Information Sciences Institute
Abstract: bellows_a.pdf

Paper D3
"FPGA Redesign of a Microprocessor-based Subsystem With No Impact to the Mission Software"
Keith Bergevin
Defense Microelectronics Activity
Abstract: bergevin_a.html, bergevin_a.pdf, bergevin_a.doc

Paper P6
"Digital Signal Processing With Altera FPGAs"
Jean-Charles Bouzigues
Altera Corporation
Abstract: bouzigues_a.pdf, bouzigues_a.doc

Paper P99
"Altera HardCopy Devices"
Jean-Charles Bouzigues
Altera Corporation
Abstract:

Paper A4
"Video Image Tracking Electronics for Advanced Video Guidance Sensor"
Tom Bryan¹, Mike Book¹, Ricky Howard¹, Greg Wirth², Steve Tate², Pat Dement³, and Jeff Green^3
1 NASA Marshall Space Flight Center
² Advanced Optical Systems, Inc.
³ Orbital Sciences Corporation
Abstract: bryan_a.pdf, bryan_a.doc

Paper P8
"Developing a MIL-STD 1553B to PCI 32/33 Bridging Applications"
Ian Bryant, Ian Land, and Ken O’Neill
Actel Corporation
Abstract: bryant_a.html, bryant_a.pdf, bryant_a.doc

Paper P85
"An ASIC-Style Methodology for FPGAs"
Dino Caporossi
Hier Design, Inc.
Abstract: caporossi_a.html

Paper P9
"Satellite and Ground Support Equipment for Space Solar Telescope"
L. Chang
National Astronomical Observatories, Chinese Academy Sciences.
Abstract: chang_a.html

Paper P10
"EEPROM Bit and Page Failure Investigation"
Yuan Chen, Rich Kemski, Duc Nguyen, Frank Stott, Ken Erickson, Leif Scheick, Richard Bennett, Tien Nguyen
Jet Propulsion Laboratory, California Institute of Technology
Abstract: chen_a.pdf

Paper P11
"Reconfigurable Avionics for Hubble Servicing Mission"
Ed Cheung¹, Will Clement², and Ray Bietry^3
1 Jackson & Tull
² Clement Engineering
³ Orbital Science Corporation
Abstract: cheung_a.pdf, cheung_a.doc

Paper P12
"Efficient Synthesis Approaches over Reconfigurable Computers"
Esmail Chitalwala¹, Tarek El-Ghazawi¹, Kris Gaj², and Nikitas Alexandridis^1
1George Washington University
²George Mason University
Abstract: chitalwala_a.pdf, chitalwala_a.doc

Paper P13
"Optimizations of Reconfigurable Systems Through the Exploitation of the Hough Transform"
Chandra Curtis¹ and John Kelly^2
1 Air Force Research Laboratory, Eglin AFB
² North Carolina A & T State University
Abstract: curtis_a.pdf, curtis_a.doc

Paper P14
"SEU Mitigation Techniques for Low-Power, High Speed Microprocessor"
David Czajkowski
Space Micro.
Abstract: czajkowski_a.html

Paper P15
"SEFI Mitigation Techniques for Microprocessors"
David Czajkowski
Space Micro.
Abstract: czajkowski_a2.html, czajkowski_a2.pdf, czajkowski_a2.doc

Paper D6
"Architecting Wide-bit Multipliers on Programmable Logic Devices"
J. P. Davis, S. Devarkal, N. Sontineni
Department of Computer Science and Engineering, University of South Carolina
Abstract: davis_a.pdf

Paper E1
"Elliptic Curve Arithmetic on Reconfigurable Hardware"
Siddaveerasharan Devarkal and Duncan A. Buell
Department of Computer Science and Engineering, University of South Carolina, Columbia
Abstract: devarkal_a.pdf, devarkal_a.doc

Paper P17
"Performance Comparison CORDIC Implementations on the SRC-6E Reconfigurable Computer"
Russ Duren, Douglas Fouts, and Dan Zulaica
Naval Postgraduate School, Monterey, California
Abstract: duren_a.pdf, duren_a.doc

Paper P79
"Actel RT54SX-S Particular Power Cycling Inrush Current Phenomena"
Daniel K. Elftmann, Solomon Wolday, Minal Sawant, Cecily Liu, and Richard Chan
Actel Corporation
Abstract: elftmann_a.html

Paper C5
"NSEU Sensitivity of SRAM-based FPGAs"
Joe Fabula, Austin Lesea, Carl Carmichael, and Saar Drimer
Xilinx Corp.
Abstract: fabula_a.html

Paper A5
"Generic Sensor Interface for On-Board Satellite Applications"
L. Fanucci¹, A. Renieri², C. Rosadini², C. Sicilia², and D. Sicilia^2
1IEIIT, National Research Council, Pisa, Italy
²Dept. of Information Engineering, University of Pisa, Pisa, Italy
Abstract: fanucci_a.pdf, fanucci_a.doc

Paper P19
"Area Array Assembly Reliability and Qualification for Spaceflight Missions"
R. Ghaffarian
Jet Propulsion Laboratory, California Institute of Technology.
Abstract: ghaffarian_a.html

Paper P20
"On the Implementation of Finite State Machines of Moderate Complexity"
Jamshid Goshtasbi-G and Arthur Alexander
Department of Electrical and Computer Engineering, Howard University
Abstract: goshtasbi_a.pdf, goshtasbi_a.doc

Paper C6
"Consequences and Categories of SRAM FPGA Configuration SEUs"
Paul Graham¹, Michael Caffrey¹, Michael Wirthlin², Eric Johnson², and Nathan Rollins^2
1 Los Alamos National Laboratory
² Brigham Young University
Abstract: graham_a.pdf

Paper P21
"Parallel Adaptive Equalizer Employing Sub-Convolution: VLSI Architecture Realized in a Field Programmable Gate Array"
Andrew A. Grary
Jet Propulsion Laboratory
Abstract: gray_a.pdf, gray_a.doc

Paper A1
"Recovery, Analysis, and Lessons Learned from the STS-107/Columbia Avionics"
Kevin Hames
NASA Johnson Space Center.
Abstract: hames_a2.html

Paper P23
"Tracking Resource Availability For Fault Tolerance and Autonomy"
Leo Hartman
Canadian Space Agency
Abstract: hartman_a.pdf, hartman_a.doc

Paper D1
"Digital Signal Processing at 1GHz in a Field-Programmable Object Array"
Dirk R. Helgemo
MathStar, Inc.
Abstract: helgemo_a.pdf, helgemo_a.doc

Paper P24
"Space Processor Radiation Mitigation and Validation Techniques for an 1,800 MIPS Processor Board"
R. Hillman, P. Layton, G. Williamson, L. Longden, C. Thibodeau, M. Conrad, and M. Giles
Maxwell Technologies
Abstract: hillman_a.html

Paper E9
"Ant Colony Systems Toolbox for Non-Combinatorial Problem Solving"
Jason C. Isaacs, Robert Watkins, Joseph Petrone, and Simon Y. Foo
Florida A&M University
Abstract: isaacs_a.pdf

Paper F1
"Field Programmable Gate Array Implementations of Cellular Automata for Pseudo-Random Number Generation"
Jason C. Isaacs, Robert K. Watkins, and Simon Y. Foo
Florida A&M University
Abstract: isaacs_a2.pdf

Paper B6
"Jitter, Power Integrity, and Proper PDS Design For FPGA Systems"
Tim Jaynes
Xilinx, Inc.
Abstract: jaynes_a.html, jaynes_a.pdf, jaynes_a.doc

Paper P26
"The Advanced Encryption Standard on the HC 36m Reconfigurable Computer"
Pradeep Kancharla and Duncan A. Buell
Department of Computer Science and Engineering, University of South Carolina
Abstract:  kancharla_a.pdf, kancharla_a.doc

Paper A2
"Review of a Mission-Critical, Digital System for an Air Force Project"
Richard B. Katz¹, Rod L. Barto¹, and Kevin Hames^2
1 NASA Office of Logic Design
² NASA Johnson Space Center
Abstract: katz_a3.html

Paper P27
"Optimum Controlling of the Systems Reliability and Readiness"
Jerzy Jazwinski, Slawomir Klimaszewski, and Józef Zurek
Air Force Institute of Technology, Warszawa, Poland.
Abstract: klimaszewski_a.pdf, klimaszewski_a.doc

Paper C3
"A Radiation Hardened by Design Approach to Solve Single Event Upsets"
David W. Jensen, Steven E. Koenck, and Alan C. Tribble
Rockwell Collins, Advanced Technology Center
Abstract: jensen_a.html, jensen_a.doc, jensen_a.pdf

Paper B1
"Giving Friend and Foe Advanced Technology: Intellectual Property in Military and Aerospace Programmable Logic Devices"
Kathleen M. Kaplan¹ and Lt Col John J. Kaplan^2
1Registered Patent Agent, United States Patent & Trademark Office and Department of Systems & Computer Science, Howard University
²Commander of the 694th Support Squadron, USAF
Abstract: kaplan_a.pdf, kaplan_a.doc

Paper P31
"On the Hilbert-Huang Transform Data Processing System Development"
Semion Kizhner¹, Thomas P. Flatley¹, Norden E. Huang¹, Karin Blank¹, Evette Conwell¹, and Darrell Smith^2
1 National Aeronautics and Space Administration, Goddard Space Flight Center
² Orbital Sciences Corporation
Abstract: kizhner_a.pdf, kizhner_a.doc

Paper P32
"Implementing a Rad-Hard Compact PCI bus-based system using Actel FPGAs"
Robert H. Klenke¹, Robert S. Hodson², and Tak-kwong Ng^2
1 SAIC
² NASA LaRC
Abstract: klenke_a.pdf, klenke_a.doc

Paper P33
"Radiation Testing Methodology for Field Programmable Gate Arrays"
Igor Kleyner¹, Richard Katz², and J.J. Wang^3
1 Orbital Sciences Corp.
² NASA Office of Logic Design
³ Actel Corporation

Paper P81
"The X-38 Spacecraft Fault-Tolerant Avionics System"
Coy Kouba¹, Deborah Buscher¹, and Joseph Busa^2
1NASA Johnson Space Center
²Charles Stark Draper Labs
Abstract: kouba_a.pdf, kouba_a.doc

Paper D7
"Flexible Arithmetic Components for Area-Efficient Fault Tolerance"
Vinu Vijay Kumar and John Lach
University of Virginia
Abstract: vijaykumar_a.pdf

Paper B5
"Power-Efficient Adaptable Wireless Sensor Networks"
John Lach, David Evans, Jon McCune, and Jason Brandon
University of Virginia
Abstract: lach_a.pdf

Paper P35
"Radiation Tolerant Single Board Computer"
Anthony Lai
Aitech Space Systems Inc.
Abstract: lai_a.pdf, lai_a.doc

Paper P36
"Radiation Effects in the Aeroflex RadHard Anti-fuse FPGA"
Ron Lake
Aeroflex Microelectronic Solutions
Abstract: lake_a.pdf

Paper D4A
"Why Software Is So Hard"
Nancy Leveson
MIT

Paper F2
"Implementation of Target Recognition Applications Using Pipelined Reconfigurable Hardware"
Ben Levine
Carnegie Mellon University
Abstract: levine_a.pdf, levine_a.doc

Paper P39
"VHDL-200X: The Future of VHDL"
Jim Lewis
SynthWorks Design Inc.
Abstract: lewis_a.html

Paper P40
"VHDL Math Tricks of the Trade"
Jim Lewis
SynthWorks Design Inc.
Abstract: lewis_a2.html

Paper P41
"Reconfigurable, Fault Tolerant and High Performance Payload for Space Missions"
Sharon Lim Siok Lin¹, Ian McLoughlin², Timo Bretschneider¹, Heiko Schröder^3
1 Satellite Engineering Centre, Nanyang Technological University, Singapore
² TAIT Electronics Ltd., Christchurch, New Zealand
³ Department of Computer Engineering, University of RMIT, Australia
Abstract: lim_a.html, lim_a.pdf, lim_a.doc

Paper E10
"Internet Worm and Virus Protection in Dynamically Reconfigurable Hardware"
John Lockwood
Washington University in Saint Louis
Abstract: lockwood_a.pdf

Paper P42
"Modeling the Requirements for Radiation Shielding: How Detailed Should It Be and When Should It Be Done"
Edward R. Long, Jr.
Longhill Technologies, Inc.
Abstract: long_a.pdf, long_a.doc

Paper P43
"Improving FPGA Application Development Using Higher Level Tools"
Eric Lord
Nallatech
Abstract: lord_a.pdf

Paper P45
"Residue Number System – based Multipliers on FPGAs"
Avinash Maddy, Simon Y. Foo and Uwe Meyer-Baese
FAMU-FSU College of Engineering
Abstract: maddy_a.pdf

Paper P46
"The Next Big Leap In Adaptive/Reconfigurable Systems"
Paul Master
QuickSilver Technology
Abstract: master_a.pdf, master_a.doc

Paper P47
"Integrated Circuit Security in Military and Commercial Systems"
John McCollum
Actel Corporation
Abstract: mccollum_a.pdf, mccollum_a.doc

Paper P48
"Breaking the IDEA Cipher Using the Star Bridge HC-36 Reconfigurable Computer"
Allen Michalski¹, Kris Gaj¹, Tarek El-Ghazawi^2
1 ECE Department, George Mason University
² ECE Department, The George Washington University
Abstract: michalski_a.pdf, michalski_a.doc

Paper P49
"Risk Averse Decisions for System Design"
Chandru Mirchandani
Lockheed-Martin Space Operations, NASA/Goddard Space Flight Center.
Abstract: mirchandani_a.html

Paper P50
"Automating Hardware Design Documentation"
Kent Moffat
Mentor Graphics Corporation
Abstract: moffat_a.pdf, moffat_a.doc

Paper P80
"Characterizing FPGA Design Practices and Methodologies"
Bharat Mody¹, Anuj Mallick¹, Nicholas Kyriakopoulos¹, Nikitas A. Alexandridis¹ and Mohamed Younis^2
1The George Washington University
²University of Maryland, Baltimore County
Abstract: mody_a.pdf

Paper P51
"Design Security in SRAM-based FPGAs"
Jason Moore
Xilinx
Abstract: moore_a.pdf, moore_a.doc

Paper P52
"FPGA Implementation of a Multilayer Maze Routing Accelerator"
John A. Nestor
Department of Electrical and Computer Engineering, Lafayette College
Abstract: nestor_a.html

Paper E2
"Optimum Implementation of Elliptic Curve Cryptosystems on the SRC-6E Reconfigurable Computer"
Nghi Nguyen¹, Kris Gaj¹, David Caliga², Tarek El-Ghazawi^3
1 George Mason University
² SRC Computers
³ The George Washington University
Abstract: nguyen_a.pdf

Paper P53
"Reconfigurable Computing: Applications of Run-time Reconfiguration"
Deepti Nipankar-Thakar and Simon Y. Foo
FAMU-FSU College of Engineering
Abstract: nipankar-thakar_a.pdf

Paper P82
"A Breakthrough Technology To Replace the Traditional PLD Marketplace"
Meged Ofer
Cellot, Inc
Abstract: ofer_a.pdf, ofer_a.doc

Paper P54
"An Autonomous Evolvable Architecture in a Reconfigurable Protocol Chip for Satellite Networks"
C. Okino, C. Lee, A. Gray, P. Arabshahi
Jet Propulsion Laboratory
California Institute of Technology
Abstract: okino_a.pdf, okino_a.doc

Paper P55
"Fault Protection in a Component-Based Spacecraft Architecture"
Elwin C Ong
Massachusetts Institute of Technology
Abstract: ong_a.html

Paper B7
"Creating Parameterized and Energy-Efficient System Generator Designs"
Jingzhao Ou, Seonil Choi, Gokul Govindu, and Viktor K. Prasanna
EE - Systems, University of Southern California
Abstract:  ou_a.pdf, ou_a.ps

Paper D2
"SIMD 2-D Convolver for Fast FPGA-based Image and Video Processors"
Stefania Perri¹, Marco Lanuzza¹, Pasquale Corsonello² and Giuseppe Cocorullo^1
1 Department of Electronics, Computer Science and Systems, University of Calabria
² Department of Computer Science, Mathematics, Electronics and Transportation, University of Reggio Calabria
Abstract: perri_a.pdf

Paper P57
"An Efficient Discrete Wavelet Transform Architecture for FPGA Implementation"
Joseph Petrone, Shonda L. Walker and Simon Y. Foo
Department of Electrical and Computer Engineering, Florida Agricultural & Mechanical University,
Abstract: petrone_a.html, petrone_a.pdf

Paper P58
"Library of Adaptive Regular Arrays for Convolution-like Computations"
Toomas Plaks
London South Bank University.
Abstract: plaks_a.pdf

Paper P59
"A linear algebra processor using Monte Carlo methods"
T. P. Plaks¹, G. M. Megson², O. Cadenas² and V. N. Alexandrov^2
1 London South Bank University
² The University of Reading, UK
Abstract: plaks_a2.pdf

Paper P60
"Hierarchical Design Space Exploration on Multiple FPGA Platforms: A Case Study"
Gang Quan
University of South Carolina
Abstract: quan_a.pdf, quan_a.doc

Paper P61
"Reliability of Hardware and Designs; Fault Tolerance"
R. Quao
Abstract:  quao_a.html

Paper P101
"Automatic Generation of Matrix Macros for FPGAs"
Anand Rajaram, Raghu Akkapeddi, and Rabi Mahapatra
Texas A&M University, College Station
Abstract: rajaram_a.html

Paper P86
"NASA/BAE SpaceWire Efforts"
Glenn Parker Rakow¹, Richard G. Schnurr¹, and Paul Kapcio^2
1NASA Goddard Space Flight Center
²BAE Systems
Abstract: rakow_a.html

Paper P62
"Demonstration of Chalcogenide Based Non Volatile Memory"
J. Rodgers¹, L. Burcin¹, J. Maimon², and K. Hunt^3
1 BAE SYSTEMS
² Ovonyx
³ AFRL/VSSE
Abstract: rodgers_a.pdf, rodgers_a.doc

Paper P63
"Evaluating TMR Techniques in the Presence of Single Event Upsets"
Nathan Rollins¹, Michael Wirthlin¹, Paul Graham², and Michael Caffrey^2
1 Brigham Young University
² Los Alamos National Laboratory
Abstract: rollins_a.pdf

Paper E5
"A Reconfigurable Computing Architecture Utilizing a Switch Fabric Network"
P. Rudolph¹, E Bentley¹, W. Turri¹, K. Hill^2
1Systran Federal Corporation, Dayton OH
²AFRL/IFTA, WPAFB, OH
Abstract: rudolph_a.pdf, rudolph_a.doc

Paper C1
"Selective Triple Modular Redundancy for SEU Mitigation in FPGAs"
Praveen Kumar Samudrala¹, Jeremy Ramos², and Srinivas Katkoori^1
1 University of South Florida
² Honeywell Space Systems Inc.
Abstract: samudrala_a.pdf

Paper P64
"When Worlds Collide: Embedded Systems in FPGAs"
Joel A. Seely
Altera Corporation
Abstract: seely_a.pdf, seely_a.doc

Paper P65
"FPGA Implementation of High Performance, Highly Pipelined and Adaptive Prediction Error Filter"
Sanjay Sharma¹, Sanjay Punjab² and R.C. Chauhan^3
1 Department of ECE, SLIET
² Department of ECE, TTTI
³SLIET, Punjab.
Abstract: sharma_a.doc

Paper P66
"FPGA-Based Implementation of Joint Channel Estimation and Data Detection over Fading Channels"
Sanjay Sharma¹, Sanjay Punjab² and R.C. Chauhan^3
1 Department of ECE, SLIET
² Department of ECE, TTTI
³SLIET, Punjab.
Abstract: sanjay_a.html, sanjay_a.pdf, sanjay_a.doc

Paper P87
"System-On-Chip Verification Methodology"
Gregor Siwinski
Aldec, Inc.
Abstract: siwinkski_a.html, siwinski_a.pdf

Paper E7
"Development of a Software Radio Based Reconfigurable Intersatellite Crosslink Testbed"
Jason A. Soloff¹, Bernard L. Edwards¹ and Scott D. Hoy^2
1 NASA Goddard Space Flight Center
² Lockheed Martin
Abstract: soloff_a.html

Paper E3
"Scientific Applications on a Reconfigurable, FPGA-based Hypercomputer"
Olaf O. Storaasli
NASA Langley Research Center
Abstract: storaasli_a.pdf, storaasli_a.doc

Paper E6
"Mapping Networking Applications To Multiprocessor-FPGA Configurable Computing Systems"
Siva Subramanian¹ and Clay S. Gloster, Jr.^2
1 Nortel Networks
² Howard University
Abstract: subramanian_a.txt

Paper P67
"Estimation of Single Event Upset Probability Impact of FPGA Designs"
 Prasanna Sundararajan¹, Cameron Patterson², Carl Carmichael¹, Scott McMillan¹, and Brandon Blodget^1
1Xilinx Inc 2100 Logic Drive San Jose, CA
²Xilinx Inc 3100 Logic Drive, Longmont, CO
Abstract: sundararajan_a.html, sundararajan_a.pdf, sundararajan_a.doc

Paper P68
"Testing FPGA devices in Space Environment"
Prasanna Sundararajan¹, Robert Wells¹, Bob Patrie¹, Michael Caffrey² and Paul Graham^2
1 Xilinx Inc
² Los Alamos National Laboratory
Abstract: sundararajan_a2.pdf, sundararajan_a2.doc

Paper P69
"Mitigating Upsets in SRAM-based FPGAs from the Xilinx Virtex 2 Family"
Gary M. Swift¹, Candice C. Yui¹, and Carl Carmichael^2
1 Jet Propulsion Laboratory / California Institute of Technology
² Xilinx Corp.
Abstract: swift_a.pdf, swift_a.doc

Paper E4
"Effective Implementation of Generic Image Processing Filters on Hybrid Reconfigurable Computers"
Mohamed Taher¹, Esam El-Araby¹, Abhishek Agarwal¹, Tarek El-Ghazawi¹, Kris Gaj²,  and Nikitas Alexandridis^1
1 The George Washington University
² George Mason University
Abstract: taher_a.pdf, taher_a.doc

Paper P70
"Embedded Computer System with Soft Core CPU for Space Application"
T.Takahara², Y.Kurahashi³, T.Mizuno¹, H.Saito¹, N.Tomita^2
1 The Institute of Space and Astronautical Science
² Musashi Institute of Technology
³ Tokyo University of Science
Abstract: takahara_a.pdf

Paper E8
"Embryonics: Bio-Inspired Self-Repairing Computing Machines"
Gianluca Tempesti, Daniel Mange, AndrŽ Stauffer
Logic Systems Laboratory, Swiss Federal Institute of Technology (EPFL)
Abstract: tempesti_a.html

Paper P72
"Implementation of a High Rate, Modular JPEG2000 Encoder in a Virtex2 FPGA"
Damon Van Buren
SEAKR Engineering Inc.
Abstract: vanburen_a.html

Paper D5
"Floating-Point Mathematical Co-Processor for a Single-Chip On-Board Computer"
Tanya Vladimirova, David Eamey, Sven Keller, Martin Sweeting
Surrey Space Centre, School of Electronics and Physical Sciences, University of Surrey
Abstract: vladimirova_a.html, vladimirova_a.pdf

Paper C4
"Soft Error Rate of FLASH based FPGA in Terrestrial Environments"
J.J. Wang¹, Brian Cronquist¹, John McCollum¹, Richard Katz², and Igor Kleyner^3
1 Actel Corporation
² NASA Office of Logic Design
³ Orbital Sciences Corp.
Abstract: wang_a.html

Paper P84
"Single Event Upset and Hardening in 0.15 µm Antifuse-Based Field Programmable Gate Array"
J.J. Wang¹, B. Cronquist¹, J. McCollum¹, S. Wolday¹, W. Wong¹, R. Katz², and I. Kleyner^3
1Actel Corporation
² NASA Office of Logic Design
³ Orbital Sciences Corp
Abstract: wang_a2.html

Paper P74
"Implementation of the Discrete Fourier Transform on a Reconfigurable Processor"
Michael J. White and Clay Gloster, Jr.
Howard University
Abstract: white_a.html

Paper P83
"Parallel RS Encoders and Decoders in SDRAM Memory for Space Applications"
Phil White¹ and Alex Kisin^2
1 ECC Technologies, Inc.
² QSS Group, Inc.
Abstract: p_white_a.html

Paper A3
"Sandia Secure Processor – a Native Java Processor"
Gregory L. Wickstrom, Brent T. Meyer, and Kwok Kee Ma
Sandia National Laboratory
Abstract: ma_a2.html, ma_a2.pdf, ma_a2.doc

Paper P75
"Critical and Reliability Aspects Shaping of Man-Automated Device Set"
Wozniak D.A.¹, Jazwninski J.², Szpytko J.^3
1 Urzad Marszalkowski, Cracow, Poland
² Air Force Institute, Warszawa, Poland
³ AGH University of Mining and Metallurgy
Abstract: szpytko_a.pdf, szpytko_a.doc

Paper P76
"Taxonomy and Evaluation of FPGA Design Tools"
Yiyi Yao¹, Indu Thomas¹, Nicholas Kyriakopoulos¹, Nikitas A. Alexandridis¹ and Mohamed Younis²
The George Washington University¹
University of Maryland, Baltimore County²
Abstract: yao_thomas_a.pdf, yao_thomas_a.doc

Paper P77
"Portable FPGA Designs with Interface Adaptive Module"
Haiqian Yu, Prof. Miriam Leeser
Northeastern University
Abstract: yu_a.pdf, yu_a.doc

Home - NASA Office of Logic Design
Last Revised: September 05, 2003
Digital Engineering Institute
Web Grunt: Richard Katz