Jason D. Lohn
NASA Ames Research Center

Ronald F. DeMara
School of Electrical Engineering and Computer Science
University of Central Florida
 

Most evolutionary approaches to fault recovery in FPGAs focus on evolving alternative logic configurations as opposed to evolving the intra-cell routing. Since the majority of transistors in a typical FPGA are dedicated to interconnect, nearly 80% according to one estimate, evolutionary fault-recovery systems should benefit by accommodating routing. In this paper, we propose an evolutionary fault-recovery system employing a genetic representation that takes into account both logic and routing configurations. Preliminary experiments were run using a software model of the Xilinx Virtex FPGA and we report on our initial results.