Abstract

The day is upon us where a synthesis tool can pipeline a multiplier for us. However if you read the fine print, pipelining is only available for a limited set of FPGA technologies. What happens when the FPGA we need to use is not one of the technologies supported by our synthesis tool? Can we get there by using a coding style?

This paper covers effective VHDL coding styles to implement a pipelined 40 bit by 40 bit multiplier. First we will look at a nominal test case, 40x40 Multiplier without any pipelining. This gives us a sense of what our technology can do and determine how much we need to work to get to a solution. Next we add registers to the output and look at the synthesis tool results. If the synthesis tool can do pipelining for our technology automatically, then we are done. The observation of this paper is that synthesis tools do pipelining only for some FPGA technologies.

Next we look at how to do the pipelining in our code. The big challenge is to write VHDL code at as high as a level as possible. If possible we want to avoid thinking in terms of bits. This leaves the tedious work for the synthesis tool and keeps our code readable. To accomplish this, the first stage of the code solution in the paper does a partial multiply followed by a register. The partial results are shifted and summed to form the final result.

Notes

The paper will consist primarily of block diagrams and code examples.