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AEROFLEX UTMC’S RELIABILITY ANALYSIS FOR ANTIFUSE FPGA’S

Ron Lake
Aeroflex UTMC
Colorado Springs, CO 80907

UT4090A variety of approaches may be taken when designing a reliability test vehicle for a radiation hardened FPGA. A typical, rushed approach would be to take any current design that actually fits within the FPGA logic cells. A marketing approach would be to create a design to highlight only the strongest features of the FPGA. A true engineering approach would be to construct a design that specifically stresses the weakest physical features of the FPGA in order to gauge its long-term reliability.

This paper discusses the Aeroflex UTMC approach for creating an engineering design to thoroughly test the physical features of the .25m m, UT6325 RadHard FPGA currently being developed. The design contains modules to address all of the major structures of the UT6325: dedicated and global clocking networks, internal logic cells, internal flip flops, I/O based flip flops, wiring segments and activated antifuses. Design features allow both the functional verification of the physical structures and the delay measurement of signal propagation through those structures.

Of interest to the FPGA designer will be the mixture of schematic capture and Verilog synthesis techniques necessary to obtain the correct design for analysis. Verilog synthesis is used to create several large, repetitive design features to densely populate the internal logic cells. Schematic capture is necessary to create specific structures that highlight certain desired tests. The fixed placement capabilities of the FPGA place and route tool are used to fix physical assignments of the critical design fragments in order to force the use of desired wiring segments and antifuse structures for analysis.

SUMMARY

The paper reviews the work performed by Aeroflex UTMC to create a reliability design for a true measure of robustness on the UT6325 RadHard FPGA.