Clay Gloster, Jr., and Esther Dickens
THE RARE PROJECT
Department of Electrical Engineering
Howard University
This paper presents a unique microcomputer architecture and assembler used for mapping applications onto reconfigurable computers. A reconfigurable computer within the context of this research is a typical high performance desktop computer with an array of field programmable gate arrays (FPGAs). A flexible microcomputer architecture that is loaded into the FPGAs is also presented. This microcomputer architecture includes a very flexible datapath containing unique function cores that are tailored for each application. The instruction set of the microcomputer allows the reuse of particular op-codes for different instructions that are loaded into the FPGA. This combination microcomputer/instruction set provides the performance of RISC processors as well as the large instruction set size offered by CISC processors. An assembler reads assembly language programs written using our instruction set and executes them directly on a reconfigurable computer.
Field Programmable Gate Arrays (FPGAs) are logic devices that offer in-circuit hardware re-programmability. At some initial time instant, a particular function (i.e. addition) can be downloaded into the FPGA and executed. At a later time instant, the same FPGA device can be used for a completely different function (i.e. multiplication) by downloading the new function into the device. Reconfigurable computing (RC) is an emerging technology that utilizes FPGAs to implement computation intensive algorithms at the hardware level. A reconfigurable computer, within the context of our research, is a general purpose processor with a high speed connection to one or more FPGAs. Since a particular hardware architecture is implemented for each application, typical RC systems can achieve acceleration rates that are several orders of magnitude faster than current desktop computers.
While using a reconfigurable computer can be effective in significantly reducing overall application execution time, much of the process is manual and requires skills in both hardware design and software development. Hardware description languages, i.e. VHDL and Verilog, are typically used to model the hardware that is developed for each application followed by extensive simulation of these models. Once the model is verified, the models are mapped onto an FPGA using commercial tools for FPGA placement and routing. Finally, software is written to download the bitstream produced from placement and routing onto the FPGA as well as to initialize memory and manage overall execution of the application.
In recent research, several tools for compilation of traditional programming language programs have been presented, however, these tools have yet to significantly impact the commercial market. These tools traditionally attempt to translate programming languages like C/C++ into an equivalent representation using a hardware description language. The major problem with these systems is that the time required for placement and routing is significant \i AND\i0 required for each iteration of the edit source/compile loop. In this scenario it would not be uncommon for a designer to change a single line of the code and subsequently be required to wait several hours for placement and routing to complete. Ofcourse, an RC system designer could potentially find that many additional errors could surface requiring this process to be repeated many times.
This paper presents research that is a part of a larger project whose goal is to develop a C/C++ compiler that is targeted for RC systems. This computer uses a library of pre-built hardware modules removing the placement and routing from the edit source/compile loop. New modules are developed off-line and the compiler is subsequently given a detailed description of the functionality of these new modules. Hence the library is dynamic in nature.
The initial infrastructure for supporting such a compiler is presented in this paper. Our approach is to develop a reconfigurable microcomputer instruction set architecture (ISA) that supports a small number of instructions that are tailored for each application. A large portion of the ISA is fixed to simplify compilation of a high level programming language description onto the system. This microcomputer architecture includes a very flexible datapath containing unique function cores that execute instructions performing floating point vector operations. Floating point data is used to facilitate system debugging and functional verification.
A function core is loaded into the ISA prior to program execution defining the instruction used for a particular op-code. Subsequently a different function core can be loaded into the ISA and the same op-code reused for a completely different instruction. Hence, there is one-to-\i n \i0 mapping of op-codes to assembly language instructions. An assembler reads assembly language programs written using our instruction set and executes them directly on a reconfigurable computer.