PROGRAMMABLE TECHNOLOGIES WEB SITE

A scientific study of the problems of digital engineering for space flight systems,
with a view to their practical solution.


2002 MAPLD International Conference

Abstracts

Kossiakoff Conference Center
The Johns Hopkins University - Applied Physics Laboratory
11100 Johns Hopkins Road
Laurel, Maryland 20723-6099

September 10-12, 2002


Paper A4
"Design and Synthesis of Small and Fast Finite Field Multipliers for FPGAs"
Gregory C Ahlquist1, Brent E. Nelson2, and Michael D. Rice2
1 Air Force Institute of Technology/LSS, Wright-Patterson AFB
2 Department of Electrical and Computer Engineering, Brigham Young University
Abstract: ahlquist_a.htm
Abstract: ahlquist_a.pdf
Abstract: ahlquist_a.doc

Paper B5
"Designing For Signal and Power Integrity in FPGA Systems"
Mark Alexander
Xilinx, Inc.
Abstract: alexander_a.htm

Paper B4
"Low Complexity Method for Detecting Configuration Upset in SRAM Based FPGAs"
Raymond J. Andraka and Jennifer L. Brady
Andraka Consulting Group, Inc.
Abstract: andraka_a.htm

Paper PAN1
"Review of the Mars Odyssey Red Team Review"
Rod Barto
Spacecraft Digital Electronics
Abstract: barto1_a.htm

Paper D2
"Reconfigurable Computing Applied to Problems in Communications Security"
Duncan A. Buell and James P. Davis
Department of Computer Science and Engineering, University of South Carolina
Abstract: bell_a.pdf

Paper A1
"Programmable Logic within NASA"
Kalynnda M. Berens
Software Assurance and Safety Engineer
SAIC contractor at the NASA Glenn Research Center
Abstract: berens_a.html
Abstract: berens_a.pdf
Abstract: berens_a.doc

Paper P14
"Verification of SHUR Macro Cell Library in a Fault Tolerant Digital Signal Processor Application"
D. Breuner, P. Coakley, S. Lutjens, and M. Rose
Jaycor
Abstract: breuner_a.pdf
Abstract: breuner_a.doc

Paper C1A
"Single Event Effects Characterization of the AD8151 Digital Cross Point Switch"
Stephen Buchner1, Paul Marshall2, Jim Howard3, Marty Carts4, Robert Reed5 and Ken LaBel5
1QSS
2Consultant
3Jackson and Tull
4Raytheon
5NASA Goddard Space Flight Center
"Stephen P. Buchner" <sbuchner@pop500.gsfc.nasa.gov>
Abstract:  buchner_a.pdf
Abstract: buchner_a.doc

Paper P4
"Radiation Hardness Improvement of the SiGe Bipolar Transistors by the Use of the Radiation & Thermal Processing (RTP- technology)"
S.V. Bytkin
Ukraine, Zaporozhye
Abstract: bytkin_a.pdf
Abstract: bytkin_a.doc

Paper A2
"A Space-Based Reconfigurable Radio"
Michael Caffrey
Los Alamos National Laboratory
Abstract: caffrey0_a.pdf

Paper P8
"Single-Event Upsets in SRAM FPGAs"
Michael Caffrey1, Paul Graham1, Eric Johnson1, and Michael Wirthlin2
1 Los Alamos National Laboratory
2 BYU
Abstract: caffrey1_a.pdf

Paper P21
"SEE and TID Extension Testing of the Xilinx XQR18V04 4Mbit Radiation Hardened Configuration PROM"
Carl Camichael1, Joe Fabula1, Gary Swift2, Steve Guertin2, and Candice Yui2
1
Xilinx, Inc.
2 Jet Propulsion Laboratory
Abstract: carmichael_a.htm
Abstract: carmichael_a.pdf
Abstract: carmichael_a.doc

Paper A5
"A Fast Transform DSP Coprocessor"
Anja Zoe Christen1, Uwe Liebstueckel1, and Laurens Bierens2
1 Astrium GmbH
2 DoubleBW Systems B.V
Abstract: christen_a.htm
Abstract: christen_a.pdf
Abstract: christen_a.doc

Paper P30
3:45 - 4:10 pm
"Coding HDL for Reviewability"
Ben Cohen
VhdlCohen Publishing
Abstract: barto0_a.htm

Paper D6
"Development of a Remotely Reconfigurable Integrated Image Processing Platform [RIP]"
Robin Coxe1, William Marinelli1, Creigh Gordon2
1Physical Sciences Inc.
2Air Force Research Laboratory (AFRL/VSSE)
Abstract: coxe_a.pdf
Abstract: coxe_a.doc

Paper E2
"Grow Your Own Circuits"
R. Timothy Edwards
Johns Hopkins University Applied Physics Lab
Tel: (240) 228-4613
Abstract: edwards_a.html

Paper C4
"Post Programming Burn In (PPBI) for RT54SXS Actel FPGAs"
Dan Elftmann and Minal Sawant
Actel Corporation
Abstract: elftmann_a.pdf
Abstract: elftmann_a.doc

Paper P20
"Update on the Qualification of PEMs (Plastic Encapsulated Microcircuits) in Space"
Joseph J Fabula
Xilinx  Corporation
Abstract: fabula_a.html
Abstract: fabula_a.pdf
Abstract: fabula_a.doc

Paper P22
"Construction Analysis of the XQVR300 FPGA and the XQR18V04 PROM"
Frederick Felt
Failure Analysis Laboratory
QSS/NASA Goddard Space Flight Center
Abstract: felt_a.html

Paper B1
"ESA FPGA Task Force: Lessons Learned"
A. Fernández-León 1, A. Pouponnot 2 and S. Habinc 3
1European Space Agency ESTEC D/TOS-ESM/AFL
2European Space Agency ESTEC D/TOS-ESD/AP
3Gaisler Research, Gothenburg, Sweden
Abstract: fernandez-Leon_a.pdf
Abstract: fernandez-Leon_a.doc

Paper D3
"Implementation Trade-offs of Triple-DES in the SRC Reconfigurable Computing Environment"
Osman Devrim Fidanci, Hatim Diab, Tarek El-Ghazawi, and Nikitas Alexandridis
Dept. of Electrical and Computer Engineering, The George Washington University
fidanci@gwu.edu
Abstract: fidanci_a.html
Abstract: fidanci_a.pdf
Abstract: fidanci_a.doc

Paper E10
"Construction of quickly operating and highly failure resisting processors of digital information processing functioning in the real time scale"
I.Furman and V.Krasnobaev
Kharkiv State Technical University
Abstract: furman_a.html

Paper P1
"Construction Principles and Architecture of a Safe, High-Performance Logic Controlling Module"
Ilia Furman and Mikhail Malinovsky
Kharkiv State Technical University.
Abstract: furman_a.pdf
Abstract: furman_a.doc

Paper E6
"A Reconfigurable Instruction Set Microcomputer"
Clay Gloster, Jr., and Esther Dickens
Department of Electrical Engineering, Howard University
Abstract: gloster_a.htm

Paper P15
"Implementation of Adaptive Digital Controllers on Programmable Logic Devices"
David A. Gwaltney, Kenneth D. King and Keary J. Smith
NASA Marshall Space Flight Center
Huntsville, AL
Abstract: gwaltney_a.htm

Paper P9
"Advanced Integrated Control and Data Systems for Constellation Satellites"
Dr. Michael Hahn, Günther Elsner
Astrium GmbH
Abstract: hahn_a.pdf
Abstract: hahn_a.doc

Paper P16
"A Reconfigurable 1.5 GB Stacked SDRAM Board"
Dr. Robert F. Hodson, Darren R. Boyd, and Mark L. Jones
NASA Langley Research Center
Abstract: hodson_a.pdf
Abstract: hodson_a.doc

Paper C1B
"Radiation Testing of Two High Speed Communication Networks"
Jim Howard1, Steve Buchner2, Paul Marshall3, Ken LaBel4, Hak Kim2, Marty Carts5, Christina Seidleck5, Ron Stattel5, Charlie Rogers5, and Tim Irwin2
1 Jackson & Tull Chartered Engineers
2 QSS, Inc.
3 Consultant
4 NASA Goddard Space Flight Center
5 Raytheon ITSS
Abstract: howard1_a.pdf
Abstract: howard1_a.doc

Paper P13
"Update on the Radiation Testing of the Pentium III Microprocessor"
Jim Howard1, Ken LaBel2, Marty Carts3, Ron Stattel3, Charlie Rogers3, and Tim Irwin4
1 Jackson & Tull Chartered Engineers
2 NASA GSFC
3 Raytheon ITSS
4 QSS, Inc.
Abstract: howard2_a.pdf
Abstract: howard2_a.doc

Paper E3
"Evolvable Random Number Generators: A Few Ants in Your Hardware could be a Good Thing"
Jason C. Isaacs, Robert K. Watkins, and Simon Y. Foo
Department of Electrical Engineering
FAMU-FSU College of Engineering
Abstract: isaacs_a.html
Abstract: isaacs_a.pdf
Abstract: isaacs_a.doc

Paper P18
"A Versatile State-Machine Controller for the SABER Instrument".
Mark D. Jensen and Jay C. Ballard
Space Dynamics Laboratory, Utah State University
Abstract: jensen_a.htm
Abstract: jensen_a.pdf
Abstract: jensen_a.doc

Paper P6
"Apollo: A Unique Project, Time, and Period in US Culture"
R. Katz
NASA Goddard Space Flight Center
Abstract: apollo_images.htm
Note: This is for exhibition in Posters Section.

Paper P11
"Compact, Low-Power Altimeter Electronics for a Deep Space Mission"
R. Katz1, I. Kleyner2, and R. Barto3
1NASA Goddard Space Flight Center
2Orbital Sciences Corporation
3Spacecraft Digital Electronics
Abstract:

Paper P2
"A Simple Algebraic Solution to Prove the Efficiency of a Bi-Elliptic Transfer Orbit Over the Hohmann Transfer Orbit"
B. Kaushik
Department of Aerospace Engineering, Indian Institute of Technology
Abstract: kaushik_a.pdf
Abstract: kaushik_a.doc

Paper P19
"An FPGA Wire Database for Run-Time Routers"
Eric Keller and Scott McMillan
Xilinx Labs
Abstract: keller_a.pdf

Paper E5
"On-Board Device and System Architectures with the Version-Thrshold Adaptation to Hardware and Software Faults"
Vyacheslav S. Kharchenko1 and V.V. Sklyar2
1Aerospace University, Ukraine
2Kharkiv Military University, Ukraine
Abstract: kharchenko_a.html
Abstract: kharchenko_a.pdf
Abstract: kharchenko_a.doc

Paper P12
"FPGA Performance vs. Specification"
I. Kleyner
Orbital Sciences Corporation

Paper P7
"SDRAM Single-Event Error Modes—Characterization, Rate Calculation and Mitigation"
Ray Ladbury
Orbital Sciences Corporation
Abstract: ladbury_a.pdf
Abstract: ladbury_a.doc

Paper C5
"Where is 'The Weakest Link?' Aeroflex UTMC’S Reliability Analysis For Antifuse FPGA’S"
Ron Lake
Aeroflex UTMC
Abstract: lake_a.html
Abstract: lake_a.pdf
Abstract: lake_a.doc

Paper P23
Henning Leidecker
"Reliability of Wire Bonds in Modern ASICs and FPGAs"
NASA Goddard Space Flight Center
Abstract: leidecker_a.html

Paper P25
"Coding a 40x40 Pipelined Multiplier"
Jim Lewis
SynthWorks Design Inc.
Abstract: lewis_a.htm
Abstract: lewis_a.pdf
Abstract: lewis_a.doc

Paper E4
"A Genetic Representation for Evolutionary Fault Recovery in FPGAs"
Jason D. Lohn1 and Ronald F. DeMara2
1 NASA Ames Research Center
2 University of Central Florida
Abstract: lohn_a.htm

Paper P10
"The Causes Behind the Random failure of Electronic Component Leads During In-Plane Vibration Testing"
Jack Lorenz
Northrup-Grumman
Abstract: lorenz_a.pdf
Abstract: lorenz_a.doc

Paper E8
"Adaptive Computing Enables High Performance and Low Power Consumption in Next-Generation Mobile and Wireless Systems"
Paul Master
QuickSilver Technology
Abstract: master_a.pdf
Abstract: master_a.doc

Paper P5
"Developing Performance Measures for New Technologies"
Chandru Mirchandani
Lockheed Martin Space Operations, NASA/Goddard Space Flight Center
Abstract: mirchandani.pdf
Abstract: mirchandani.doc

Paper P17
"Application of Reconfigurable Computing Technology to Multi-KiloHertz Micro-Laser Altimeter (MMLA) Data Processing"
Wesley Powell, Philip Dabney, Edward Hicks, and Maxime Pinchinat
NASA Goddard Space Flight Center
Abstract: powell_a.htm
Abstract: powell_a.pdf
Abstract: powell_a.doc

Paper B3
"Accelerating Image Processing Pipelines in a Hardware/Software Environment"
Heather Quinn, Miriam Leeser, and Laurie Smith King
Northeastern University
College of the Holy Cross
Northeastern University
Abstract: quinn_a.htm
Abstract: quinn_a.pdf
Abstract: quinn_a.doc

Paper P26
"Easily Designed ASICs for Flip Chip Applications"
William Devanney, John MacPherson, and David Schmulian
Clear Logic, Inc.
Abstract: schmulian_a.htm
Abstract: schmulian_d.pdf

Paper A3
"Energy-Efficient Design of Kernel Applications for FPGAs Through Domain-Specific Modeling
Ronald Scrofano, Seonil Choi, and Viktor K. Prasanna
Department of Electrical Engineering-Systems, University of Southern California
Viktor K. Prasanna
Abstract: scrofano_a.pdf
Abstract: scrofano_a.ps

Paper E1
"Evolution-enabled Reconfigurable Computing using Field-Programmable Analog Devices"
Adrian Stoica1, Xin Guo2, Ricardo S. Zebulum1, M. I. Ferguson1, Didier Keymeulen1, and Taher Daud1
1Jet Propulsion Laboratory Pasadena, CA 91109
2Chromatech, Alameda CA 94501
Abstract: stoica_a.htm

Paper D1
"Scientific Computations on a NASA Reconfigurable Hypercomputer"
Olaf O. Storaasli1, Robert C. Singleterry1, and Sam Brown2
1 NASA Langley, Hampton VA
2 Star Bridge Systems, Midvale UT
Abstract: storaasli_a.pdf
Abstract: storaasli_a.doc

Paper E11
"A Configurable Architecture for High-Speed Communication Systems"
Visvanathan Subramanian, Joseph G. Tront, Charles W. Bostian, Scott F. Midkiff
Center for Wireless Telecommunication, Virginia Polytechnic Institute and State University,
Abstract: subramanian_a.htm
Abstract: subramanian_a.pdf
Abstract: subramanian_a.doc

Paper P29
"Single-Event Upset Susceptibility Testing of the Xilinx Virtex II FPGA"
Gary Swift1, Candice Yui1, and Carl Carmichael2
1Jet Propulsion Laboratory / California Institute of Technology, Pasadena, CA
2Xilinx, Inc., San Jose, CA
Abstract: swift_a.htm
Abstract: swift_a.pdf
Abstract: swift_a.doc

Paper P27
"Job Management System Extension to Support SLAAC-1V Reconfigurable Hardware"
Mohamed Taher1, Kris Gaj2, Tarek El-Ghazawi1, and Nikitas Alexandridis1
1 The George Washington University
2 George Mason University
mtaher@seas.gwu.edu
202 994 7309 (Phone)
Abstract: taher_a.pdf
Abstract: taher_a.htm

Paper B6
"Improving Detectability of Resistive Open Defects in FPGA"
Mehdi Baradaran Tahoori and Edward J. McCluskey
Center for Reliable Computing
Stanford University
Abstract: tahoori_a.pdf

Paper E7
"Embedded Computer System with Soft Core CPU for Space Application"
T.TakaharaB, Y.KurahashiC, T.MizunoA, H.SaitoA, N.TomitaB
A The Institute of Space and Astronautical Science
B Musashi Institute of Technology, C Tokyo University of Science

Abstract: takahara_a.pdf
Abstract: takahara_a.doc

Paper P28
"Where Hardware is Really Software"
Jim Tomayko
Carnegie Mellon University
"Jim Tomayko" <jet@cs.cmu.edu>
Abstract: tomayko_a.html
Abstract: tomayko_a.pdf
Abstract: tomayko_a.doc

Paper E9
"A Hardware Debugging Environment for FPGA-Based Systems"
Karen A. Tomko and Faisal Muslehuddin
Department of Electrical and Computer Engineering and Computer Science
University of Cincinnati
Paper Withdrawn.

Paper P3
"A Fault Modeling Technique to test Memory BIST Algorithms"
Raja Venkatesh, Sailesh Kumar, Joji Philip, Sunil Shukla
PaXonet Communications
Abstract: venkatesh_a.pdf

Paper C2
"Single Event effects of 0.15µm Antifuse FPGA"
J. J. Wang1, B. Cronquist1, J. McCollum1, I. Kleyner2, and R. Katz3
1 Actel Corp, Sunnyvale, CA 94085
2 Orbital Science Corp, Greenbelt, MD 20771
3 NASA/GSFC, Greenbelt, MD 20771
Abstract: wang_a.pdf
Abstract: wang_a.doc

Paper C3
"Reliability of Programmable Input/Output Pins in the Presence of Configuration Upsets"
Michael Wirthlin1, Nathan Rollins1, Michael Caffrey2, and Paul Graham2
1 BYU
2 Los Alamos National Laboratory
Abstract: wirthlin_a.pdf

Paper D5
"A CCSDS-Based Communication System for a Single Chip On-Board Computer"
Daixun Zheng,  Tanya Vladimirova, and Martin Sweeting
Surrey Space Centre, University of Surrey
Abstract: zheng_a.htm
Abstract: zheng_a.pdf
Abstract: zheng_a.doc

Paper B2
"Implementation of Gigahertz 1-bit Full Adder on SiGe FPGA"
K. Zhou, Channakeshav, R. Kraft, J. F. McDonald
Rensselaer Polytechnic Institute
Abstract: zhou_a.pdf


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