Tutorial Courses and Seminars
The 2001 MAPLD International Conference Seminars
Hi,
The 2002 MAPLD International Conference is offering two seminars on September 9, 2002. You may sign up for a seminar using the registration form on the Registration Page.
The 2002 class formats will differ from 2001. One seminar will be approximately 3 hours long, given in the morning; the other will be 6 hours long, and run over the course of the day. 15-20 minute breaks will be provided.
Seminars for the 2002 MAPLD International Conference:
Logic Design: Clocking, Timing Analysis, Finite State Machines, and Verification (6 hours, full day).
9 am to 12 noon; 1 - 4 pm
Abstract
The fundamental theme of this seminar will be the design and verification finite state machines for high-reliability applications. The starting point for any synchronous sequential circuit design and analysis is the clock. Clock structures and characteristics, both at the device and application level, will be discussed and their impact on circuit topologies and timing analysis. Starting with the straightforward single-phase, single-edge, low-skew global clocks, different clock structures will be explored for different design goals such as low-power and high-speed. Finite state machines will be covered in detail from two perspectives: the topologies logic as well as applications. Examples of topologies to be covered will include Gray, one-hot, sequential, LFSR, and others. Applications to be covered include synchronizers, arbiters, controllers, and others. Analysis will be performed to determine the robustness of each solution. The results of the analysis will lead to a discussion of error detection and correction and the trade-offs; e.g., some circuits have a higher probability of error but permit 100% detection of all single bit errors. A discussion of error detection and correction methods will show various techniques as well as trade-offs. For example, should the monitoring circuits be located at the lowest possible level or the system level? This will be shown to be a function of the state machine's structure and circuit application.
Programmable Logic in the Radiation Environment (3 hours, morning).
9 am to 12 noon
Abstract
Missions for the space environment differ from those of many terrestrial applications since they are presented with a radiation environment and long life requirements. Additionally, maintenance operations are extremely expensive if possible at all. The fundamentals of the radiation environment and radiation test techniques will be reviewed. Detailed specifications and failure modes will be analyzed, for each class of device and technology. Figures of merit will be given for specific devices in use. Design techniques to provide reliable operation in the radiation environment will be discussed as well as the analysis of device reliability issues such as single point failures and how to avoid them.
Thanks,
We hope to see you at MAPLD 2002,
Richard B. Katz
National Aeronautics and Space Administration
Seminar Instructors
Richard B. Katz
National Aeronautics and Space Administration
Rod L. Barto
Spacecraft Digital Electronics
Kenneth A. LaBel
National Aeronautics and Space Administration
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Last Revised: August 27, 2002
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